PIMXRT406LCVL4A datasheet(49/100 Pages) NXP

49 / 100 page

Electrical characteristics

i.MX RT1020 Crossover Processors for Industrial Products, Rev. 2, 03/2021

NXP Semiconductors

NOTE

CSS and TCSH are configured by the FlexSPIn_FLSHAxCR1

RT1020 Reference Manual (IMXRT1020RM) for more details.

Figure 25. FlexSPI output timing in SDR mode

4.5.2.2.2

DDR mode

NOTE

CSS and TCSH are configured by the FlexSPIn_FLSHAxCR1

RT1020 Reference Manual (IMXRT1020RM) for more details.

TCSS

Chip select output setup time

3 x TCK -1

—

TCSH

Chip select output hold time

3 x TCK + 2

—

1 The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to the FlexSPI SDR input timing

specifications.

Table 45. FlexSPI output timing in DDR mode

Symbol

Parameter

Min

Max

Unit

—

Frequency of operation1

1 The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to the FlexSPI SDR input timing

specifications.

—166

MHz

Tck

SCK clock period (FlexSPIn_MCR0[RXCLKSRC] = 0x0)

6.0

—

TDVO

Output data valid time

—

2.2

TDHO

Output data hold time

0.8

—

TCSS

Chip select output setup time

3 x TCK / 2 - 0.7

—

TCSH

Chip select output hold time

3 x TCK / 2 + 0.8

—

Table 44. FlexSPI output timing in SDR mode (continued)

Symbol

Parameter

Min

Max

Unit

T CSS

T CK

TCSH

TDVO

TDHO

TDVO

TDHO

SCK

SIO[0:7]

PIMXRT406LCVL4A Datasheet(PDF) 49 Page - NXP Semiconductors

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