PIMXRT406LCJM4A datasheet(74/100 Pages) NXP

74 / 100 page

i.MX RT1020 Crossover Processors for Industrial Products, Rev. 2, 03/2021

NXP Semiconductors

Boot mode configuration

This section provides information on boot mode configuration pins allocation and boot devices interfaces

allocation.

5.1

Boot mode configuration pins

Table 67 provides boot options, functionality, fuse values, and associated pins. Several input pins are also

sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.

The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an

unblown fuse). For detailed boot mode options configured by the boot mode pins, see the i.MX RT1020

Fuse Map document and the System Boot chapter in i.MX RT1020 Reference Manual (IMXRT1020RM).

5.2

Boot device interface allocation

The following tables list the interfaces that can be used by the boot process in accordance with the specific

boot mode configuration. The tables also describe the interface’s specific modes and IOMUXC allocation,

which are configured during boot when appropriate.

Table 67. Fuses and associated pins used for boot

Pad

Default setting on reset

eFuse name

Details

GPIO_EMC_16

100 K pull-down

src.BOOT_MODE0

GPIO_EMC_17

100 K pull-down

src.BOOT_MODE1

GPIO_EMC_18

100 K pull-down

src.BT_CFG[0]

Boot Options, Pin value overrides fuse

settings for BT_FUSE_SEL = ‘0’.

Signal Configuration as Fuse Override

Input at Power Up.

These are special I/O lines that control

the boot up configuration during

product development. In production,

the boot configuration can be

controlled by fuses.

GPIO_EMC_19

100 K pull-down

src.BT_CFG[1]

GPIO_EMC_20

100 K pull-down

src.BT_CFG[2]

GPIO_EMC_21

100 K pull-down

src.BT_CFG[3]

GPIO_EMC_22

100 K pull-down

src.BT_CFG[4]

GPIO_EMC_23

100 K pull-down

src.BT_CFG[5]

GPIO_EMC_24

100 K pull-down

src.BT_CFG[6]

GPIO_EMC_25

100 K pull-down

src.BT_CFG[7]

GPIO_EMC_26

100 K pull-down

src.BT_CFG[8]

GPIO_EMC_27

100 K pull-down

src.BT_CFG[9]

Table 68. Boot trough NAND

PAD Name

IO Function

ALT

Comments

GPIO_EMC_00

semc.DATA[0]

ALT 0

—

GPIO_EMC_01

semc.DATA[1]

ALT 0

—

GPIO_EMC_02

semc.DATA[2]

ALT 0

—

GPIO_EMC_03

semc.DATA[3]

ALT 0

—

GPIO_EMC_04

semc.DATA[4]

ALT 0

—

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