STV82X8 datasheet(37/157 Pages) STMICROELECTRONICS

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STV82x8

I²S Interface (In / Out)

6.1.2

I²S Inputs in TQFP 100 Package

An additional (auxiliary) asynchronous input is available in the TQFP100 package. An I2SD_DATA

input for external delay is also available, but it must be in phase with the I²S output clocks.

6.2

I²S Outputs

6.2.1

I²S Outputs in TQFP 80 Package

A digital stereo output (I²S compatible) is also available for routing the demodulated signal or a

converted input audio signal to an external device. In this case, the I2S_DATA0 signal and all clock

signals are set as outputs by setting bit D5 in register RESET to 1 (and bit D6 for the clocking). The

STV82x8 drives the serial bus (I2S_SCLK, I2S_LR_CLK, and I²2S_DATA0) in master mode in 64.fs

format with a sampling frequency (fs) of 48 kHz. The I2S_PCM_CLK signal can be used as a master

clock for the slave interface, if required. Both standard and non-standard modes are available.

Figure 26: TQFP100 I²S Input Block Diagram

Audio Processing

I2S_DATA0

I2S_DATA1

I2S_DATA2

fS Input = 32 to 48 kHz

fS Input = 48 kHz only

I2S_SCLK

I2S_LR_CLK

fS Input = 32 to 48 kHz

fS Input * 64

48 kHz DSP

Processing

I2SA_DATA

fS Input = 32 to 48 kHz

I2SA_SCLK

I2SA_LR_CLK

fS Input = 32 to 48 kHz

fS Input * 64

I2SD_DATA

fS Input = 48 kHz in phase with I2SO_LR_CLK and I2SO_SCLK

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