Preliminary Technical Data

AD7792/AD7793

REV.PrF 6/04 | Page 13

STATUS REGISTER (RS2, RS1, RS0 = 0, 0, 0; POWER-ON/RESET = 0x80 (AD7792) / 0x88 (AD7793))

The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register,

select the next operation to be a read, and load bits RS2, RS1 and RS0 with 0. Table 7 outlines the bit designations for the status register.

SR0 through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The

number in brackets indicates the power-on/reset default status of that bit.

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

RDY(1)

ERR(0)

0(0)

0(0)

0/1

CH2(0)

CH1(0)

CH0(0)

Table 7. Status Register Bit Designations

Bit Location

Bit Name

Description

SR7

RDY

Ready bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically

after the ADC data register has been read or a period of time before the data register is updated with a

new conversion result to indicate to the user not to read the conversion data. It is also set when the part

is placed in power-down mode. The end of a conversion is indicated by the DOUT/RDY pin also. This pin

can be used as an alternative to the status register for monitoring the ADC for conversion data.

SR6

ERR

ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written

to the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange,

underrange. Cleared by a write operation to start a conversion.

SR5-SR4

0

These bits are automatically cleared.

SR3

0/1

This bit is automatically cleared on the AD7792 and is automatically set on the AD7793.

SR2–SR0

CH2–CH0

These bits indicate which channel is being converted by the ADC.

MODE REGISTER (RS2, RS1, RS0 = 0, 0, 1; POWER-ON/RESET = 0x000A)

The mode register is a 16-bit register from which data can be read or to which data can be written. This register is used to select the oper-

ating mode, update rate and clock source. Table 8 outlines the bit designations for the mode register. MR0 through MR15 indicate the bit

locations, MR denoting the bits are in the mode register. MR15 denotes the first bit of the data stream. The number in brackets indicates

the power-on/reset default status of that bit. Any write to the setup register resets the modulator and filter and sets the RDY bit.

MR15

MR14

MR13

MR12

MR11

MR10

MR9

MR8

MD2(0)

MD1(0)

MD0(0)

0(0)

0(0)

0(0)

0(0)

0(0)

MR7

MR6

MR5

MR4

MR3

MR2

MR1

MR0

CLK1(0)

CLK0(0)

0(0)

0(0)

FS3(1)

FS2(0)

FS1(1)

FS0(0)

Table 8. Mode Register Bit Designations

Bit Location

Bit Name

Description

MR15–MR13

MD2–MD0

Mode Select Bits. These bits select the operational mode of the AD7792/AD7793 (See

Table 9).

MR12-MR8

0

These bits must be programmed with a Logic 0 for correct operation.

MR7-MR6

CLK1-CLK0

These bits are used to select the clock source for the AD7792/AD7793. Either on on-chip 64 kHz clock

can be used or an external clock can be used. The ability to override use an external clock is useful as it

allows several AD7792/AD7793 devices to be synchronised. Also, 50 Hz/60 Hz is improved when an

accurate external clock drives the AD7792/AD7793.

CLK1

CLK0

ADC Clock Source

0

0

Internal 64 kHz Clock, Internal Clock is not available at the CLK pin

0

1

Internal 64 kHz Clock. This clock is made available at the CLK pin

1

0

External 64 kHz Clock used. An Exernal clock gives better 50 Hz/60 Hz rejection. The

external clock can have a 45:55 duty cycle.

1

1

External Clock used. This external clock is divided by 2 within the AD7792/AD7793.

This allows the user to supply a clock which has a duty cycle worse than a 45:55 duty

cycle to the AD7792/AD7793, for example, a 128 kHz clock.

MR5-MR4

0

These bits must be programmed with a Logic 0 for correct operation.