HMC8342LS6 datasheet(5/11 Pages) AD

5 / 11 page

Data Sheet

HMC8342

Rev. A | Page 5 of 11

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NOTES

1. EXPOSED PAD. THE EXPOSED PAD OR GROUND PADDLE

ON THE BACKSIDE OF THE PACKAGE MUST BE TIED TO

RF OR DC GROUND FOR ELECTRICAL, MECHANICAL,

AND THERMAL REASONS.

HMC8342

VGG2

VGG1

VDD3

VDD2

NIC

VDD1

Figure 2. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1 to 3

VDD3, VDD2, VDD1

Power Supply Voltage. 5 V ± 5%. Place three parallel capacitors as close as possible to each of the VDD1,

VDD2, and VDD3 pins: 4.7 μF, 10 nF, and 100 pF.

4, 8, 10, 12, 16

NIC

Not Internally Connected. These pins can be connected to RF or dc ground without affecting the

performance.

5, 7, 13, 15

GND

Ground.

RFIN

RF Input. The RFIN pin is ac-coupled and matched to 50 Ω.

9, 11

VGG1, VGG2

Gate Control for Active Multiplier. Place three parallel capacitors as close as possible to each of the VGG1

and VGG2 pins: 4.7 μF, 10 nF, and 100 pF. VGG1 (−1.25 V ± 5%) and VGG2 (−0.8 V ± 5%) must be applied

before application of VDD1, VDD2, and VDD3. See the Applications Information section for more information.

RFOUT

RF Output. The RFOUT pin is ac-coupled and matched to 50 Ω.

Exposed Pad. The exposed pad or ground paddle on the backside of the package must be tied to RF or

dc ground for electrical, mechanical, and thermal reasons.

INTERFACE SCHEMATICS

GND

Figure 3. GND Interface Schematic

GND

Figure 4. EP Interface Schematic

VDD1, VDD2, VDD3

Figure 5. VDDx Interface Schematic

RFIN

Figure 6. RFIN Interface Schematic

VGG1,

VGG2

Figure 7. VGGx Interface Schematic

RFOUT

Figure 8. RFOUT Interface Schematic

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