V103

V103 Datasheet

8

11/23/06

Revision 2.0

Integrated Circuit Systems • 525 Race St reet, S an Jose, CA 95126 • tel (408) 297-1201 • ww w. icst. com

AC Timing Diagrams

TTL Input

5 pF

100 ohms

LVDS Output

20%

20%

10%

10%

80%

80%

90%

90%

CLK IN

TA+

TA-

CLK IN

VCC/2

VCC/2

VCC/2

VCC/2

VCC/2

VOC

Tx0-Tx6

TCLK+

TCLK-

Note: CLK IN: for R/F = GND, denote as solid line.

for R/F = VCC, denote as dashed line

TTL Inputs