LTC6948 datasheet(12/26 Pages) AD

12 / 26 page

LTC5556

Rev 0

For more information www.analog.com

PIN FUNCTIONS

GND (Pins 1, 8, 9, 16, 25, 32, Exposed Pad Pin 33):

Ground. These pins must be soldered to the RF ground

plane on the circuit board. The exposed pad provides

both electrical ground contact and thermal contact to the

printed circuit board.

RF1, RF2 (Pins 2, 7): Single-Ended RF Inputs for

Channels 1 and 2, Respectively. These pins are internally

biased to VCC/2 when VCC is applied. Therefore, a series

DC-blocking capacitor must be used.

CSB (Pin 3): Serial Port Chip Select. This CMOS input

activates the SPI inputs when driven low. When driven

high, the inputs are deactivated. See the Applications sec-

tion for more details.

CLK (Pin 4): Serial Port Clock. This CMOS input

clocks serial port input data on its rising edge. See the

Applications section for more details.

SDI (Pin 5): Serial Port Data Input. This CMOS input is

used to load serial data into the 16-bit register. See the

Applications section for more details.

SDO (Pin 6): Serial Port Data Output. This CMOS three-

state output presents data from the serial port during

a communication burst. Optionally, attach a resistor

of >200k to GND to prevent a floating output. See the

Applications section for more details.

MO2–, MO2+, MO1+, MO1– (Pins 10, 11, 30, 31): Open-

Collector Differential IF Outputs for Mixer 2 and Mixer

1, Respectively. These pins must be connected to VCC

through pull-up inductors. Typical DC current is 28mA

into each pin.

VCC2, VCC1 (Pins 12, 29): Power Supply Pins for Channels

2 and 1, Respectively. These pins must be connected to

a regulated 3.3V supply, with a bypass capacitor located

close to the pins. Typical DC current consumption is

40mA into each pin.

EN2, EN1 (Pins 13, 28): Enable Control Pins for Channels

2 and 1, Respectively. A CMOS logic high will enable each

channel. These pins have internal 330k pull-down resis-

tors, so if unconnected, both channels are shutdown.

AI2+, AI2–, AI1–, AI1+ (Pins 14, 15, 26, 27): Differential

IF Attenuator Inputs for Channel 2 and Channel 1,

Respectively. These pins are internally biased to VCC/2

when VCC is applied. Therefore, a series DC-blocking

capacitor must be used.

IF2+, IF2–, IF1–, IF1+ (Pins 17, 18, 23, 24): Open-

Collector Differential IF Buffer Outputs for Channel 2 and

Channel 1, Respectively. These pins must be connected

to VCC through pull-up inductors. Typical DC current is

47mA into each pin.

RP (Pin 19): Reduced Power Select Pin. A CMOS logic

low on this pin commands both channels to full power

mode, unless programmed to reduced power mode by

the SPI. A CMOS logic high programs both channels to

reduced power mode, independent of the SPI. This pin

has an internal 330k pull-down resistor.

LO–, LO+ (Pins 20, 21): Differential Local Oscillator Input.

These pins are internally connected to ESD diodes to

ground. Therefore, series DC-blocking capacitors must

be used if the LO source has a DC voltage present. Single-

ended or differential drive may be used. Each pin is inter-

nally matched to 50Ω, even when the mixers are disabled.

VDD (Pin 22): Power Supply Pin for Serial Interface Logic.

This pin must be connected to a regulated 1.8V to 3.3V

supply. Typical DC current consumption is less than 1mA

with CSB low and the clock running at 10MHz. When

idle, typical current consumption is less than 500μA. The

supply voltage on this pin defines the logic levels for the

SPI inputs (CSB, CLK and SDI), the SDO output, and the

RP pin.

LTC6948 Datasheet(PDF) 12 Page - Analog Devices

LTC6948 Datasheet(HTML) 12 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Datasheet Download

Link URL