LTC6948 datasheet(20/26 Pages) AD

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LTC5556

Rev 0

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APPLICATIONS INFORMATION

Enable Inputs

Figure 13 shows a schematic of the Channel 1 enable

interface. Channel 2 is identical and not shown. As shown,

the positive ESD diodes for EN1 are connected to VCC1.

The positive ESD diodes for channel 2 are connected to

VCC2 (not shown). To enable a channel, the applied volt-

age must be greater than 1.4V. An applied voltage less

than 0.5V will disable the channel. If the enable function

is not needed, the enable pin can be connected directly to

the adjacent VCC pin. If left floating, the internal 330kΩ

pull-down resistor will disable the channel.

The voltage on the enable pins should never exceed VCC

by more than 0.3V, otherwise supply current may be

sourced through the upper ESD diodes. Under no cir-

cumstances should voltage be applied to the enable pins

before supply voltage is applied to the VCC pins. If this

occurs, damage to the IC may result.

SPI DESCRIPTION

IF DVGA attenuator control and reduced power mode for

each downconverter channel is programmed through the

3-wire SPI consisting of CSB, CLK and SDI. A fourth pin,

SDO, is a serial output available to read out the contents

of the registers. The SDO pin may also be used to daisy-

chain multiple SPI interfaces on a single bus. For exam-

ple, in an 8-channel MIMO receiver application, all four

LTC5556 dual downconverters can be programmed with

a single, 64-bit load, while sharing a common CSB line.

A block diagram of the SPI is shown in Figure 14. As

shown, it is a 16-bit double-buffered FIFO slave architec-

ture, with 8-bits for each channel. Logic levels for the digi-

tal inputs and SDO output are 1.8V to 3.3V CMOS com-

patible, determined by the supply voltage on the VDD pin.

An internal POR (power-on-reset) connected to the VDD

pin, resets all 16 bits to logic 0 at power-up, or when VDD

drops below 0.5V and then rises back above 1.2V. The

POR requires approximately 100μs to reset the registers.

SPI PROGRAMMING

Data transfers to the part are accomplished by first tak-

ing CSB low to enable the port. Then, serial input data

on SDI is captured on the rising edge of CLK and shifted

into a 16-bit shift register, MSB first. Serial data from the

registers is driven out to SDO on the clock’s falling edge.

The communication burst is terminated by taking CSB

high. The rising edge on CSB will then latch the shift-

latch prevents the downconverter’s gain and power mode

from changing while data is loaded. See Figure 15 for

timing details.

When CSB is high, the clock and data inputs are inter-

nally gated off, minimizing current consumption when not

selected, and the SDO output is high impedance. However,

it is recommended that the serial interface signals should

remain idle between data transfers to avoid digital noise

coupling into the RF signal paths.

Supply Voltage Ramping

Fast ramping of the supply can cause a current glitch in

the internal ESD protection circuits. Depending on the

supply inductance, this could result in a supply voltage

transient that exceeds the maximum rating. A supply volt-

age ramp time greater than 1ms is recommended.

Supply voltage for VCC1, VCC2 (Pins 29 and 21) and the

IF amplifiers (Pins 17, 18, 23 and 24) are connected on

the evaluation board, which assures that they all ramp up

and down at the same rate. If they are powered indepen-

dently in the final application circuit, care must be taken

to assure that the IF amplifier supply pins go high before

the VCC pins, and go low after the VCC pins.

Figure 13. Channel 1 Enable Pin Interface

5556 F13

VCC1

EN1

250

330k

CH 1

BIAS

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