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LTC6948 Datasheet(PDF) 16 Page - Analog Devices

Part # LTC6948
Description  1.5GHz to 7GHz Dual Programmable Gain Downconverting Mixer
PDF  26 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LTC6948 Datasheet(HTML) 16 Page - Analog Devices

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LTC5556
16
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
LO Input
A simplified schematic of the LO input is shown in Figure 5.
As shown, each mixer has its own LO amplifier. A differen-
tial input is provided although the IC is characterized and
production-tested with single-ended drive. Differential LO
drive improves performance slightly, and is recommended
if available. Each LO input is internally matched to 50Ω
from 500MHz to 8GHz, requiring no external components.
ESD protection diodes on each input limit the peak volt-
age swing to approximately ±700mV (+7dBm), although
higher LO drive, up to 10dBm will not damage the input.
An external DC-blocking capacitor is only needed if the LO
source has DC voltage present. The measured LO input
return loss is shown in Figure 6.
Figure 5. LO Input Schematic
Figure 6. LO Input Return Loss
IF Outputs
A simplified IF output schematic for channel 1, with exter-
nal matching components is shown in Figure 7 (chan-
nel 2 is identical, and not shown). The final output stage
is differential, open-collector with integrated matching
resistors, capacitors and ESD protection diodes. Each
output pin must be biased at the supply voltage (VCC)
using external chokes (L11 and L13). Each pin draws
approximately 47mA of DC supply current (94mA total).
Therefore, inductors with low DC resistance (<1Ω), are
required for the highest output IP3 and P1dB.
The integrated output resistors set the differential output
resistance at 206Ω. C3, L15 and L17 form a 2:1 imped-
ance transformer which transforms the output to 100Ω
differential. If a 200Ω output is desired, C3 is not used
and the values of L15 and L17 are reduced to the values
shown in Table 1. C9 and C11 are DC-blocking capacitors,
which may be omitted if the following stage is already
DC-blocked.
Figure 7. IF Output Schematic
5556 F05
CH 1 MIX
LO–
LO+
LO
(0dBm)
DC
BLOCK
CH 2 MIX
21
20
+
–
5556 F07
IF1+
L11
L13
L15
C9
C3
IF1OUT
C11
L17
IF1–
VCC
VCC
VCC
24
23
TC = 25°C
NO EXTERNAL MATCH
LO FREQUENCY (GHz)
0
1
2
3
4
5
6
7
8
–18
–15
–12
–9
–6
–3
0
5556 F06



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