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VS6624P0LP Datasheet(PDF) 38 Page - STMicroelectronics |
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VS6624P0LP Datasheet(HTML) 38 Page - STMicroelectronics |
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38 / 100 page ![]() Host communication - I²C control interface VS6624 38/100 Rev 1 10.3 Data valid The data on SDA is stable during the high period of SCL. The state of SDA is changed during the low phase of SCL. The only exceptions to this are the start (S) and stop (P) conditions as defined below. (See I²C slave interface for full timing specification). Figure 22. SDA data valid 10.4 Start (S) and Stop (P) conditions A START (S) condition defines the start of a V2W message. It consists of a high to low transition on SDA while SCL is high. A STOP (P) condition defines the end of a V2W message. It consists of a low to high transition on SDA while SCL is high. After STOP condition the bus is considered free for use by other devices. If a repeated START (Sr) is used instead of a stop then the bus stays busy. A START (S) and a repeated START (Sr) are considered to be functionally equivalent. Figure 23. START and STOP conditions SDA SCL Data line stable Data valid Data change Data line stable Data valid START condition STOP condition S P SDA SCL |
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