68HC705JB4 datasheet(35/134 Pages) FREESCALE

35 / 134 page

February 24, 1999

GENERAL RELEASE SPECIFICATION

MC68HC05JB4

INTERRUPTS

MOTOROLA

REV 2

4-5

The IRQE enable bit controls whether an active IRQF ﬂag can generate an IRQ

interrupt sequence. This interrupt is serviced by the interrupt service routine

located at the address speciﬁed by the contents of $1FFA and $1FFB.

If IRQF is set, the only way to clear this ﬂag is by writing a logic one to the IRQR

acknowledge bit in the ICSR. As long as the output state of the IRQF ﬂag bit is

active the CPU will continuously re-enter the IRQ interrupt sequence until the

active state is removed or the IRQE enable bit is cleared.

Figure 4-3. External Interrupt (IRQ) Logic

4.5.2 External Interrupt IRQ2

The IRQ2/PA4 pin provides an asynchronous interrupt to the CPU. When a nega-

tive-edge is detected by the schmitt trigger input, an IRQ2 interrupt will be gener-

ated if the IRQ2E-bit in the ICSR register is set. This interrupt is serviced by the

interrupt service routine located at the address speciﬁed by the contents of $1FFA

and $1FFB. A block diagram of the IRQ2 function is shown in Figure 4-4.

IRQ

LATCH

VDD

RST

IRQ VECTOR FETCH

IRQ STATUS/CONTROL REGISTER

EXTERNAL

INTERRUPT

REQUEST

INTERNAL DATA BUS

TO BIH & BIL

INSTRUCTION

PROCESSING

IRQ Level

(Mask Option)

PA0

PA1

PA2

PA3

Port A External Interrupt

(Mask Option)

Freescale Semiconductor, Inc.

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