68HC705JB4 datasheet(41/134 Pages) FREESCALE

41 / 134 page

February 24, 1999

GENERAL RELEASE SPECIFICATION

MC68HC05JB4

RESETS

MOTOROLA

REV 2

5-3

The POR will generate the RST signal which will reset the CPU. If any other reset

function is active at the end of the 4064 cycle delay, the RST signal will remain in

the reset condition until the other reset condition(s) end.

POR will not activate the pulldown device on the RESET pin. VDD must drop

below VPOR in order for the internal POR circuit to detect the next rise of VDD.

5.3.2 USB Reset

The USB reset is generated by a detection on the USB bus reset signal. For

MC68HC05JB4, seeing a single-end zero on its upstream port for 4 to 8 bit times

will set RSTF bit in UIR0 register. The detections will also generate the RST signal

to reset the CPU and other peripherals in the MCU.

5.3.3 Computer Operating Properly (COP) Reset

The COP watchdog is enabled by a mask option.

A timeout of the COP watchdog generates a COP reset. The COP watchdog is

part of a software error detection system and must be cleared periodically to start

a new timeout period. To clear the COP watchdog and prevent a COP reset, write

a logic zero to the COPC bit of the COP register at location $1FF0.

COPC — COP Clear

COPC is a write-only bit. Periodically writing a logic zero to COPC prevents the

COP watchdog from resetting the MCU. Reset clears the COPC bit.

1 =

No effect on system.

0 =

Reset COP watchdog timer.

The COP Watchdog reset will assert the pulldown device to pull the RESET pin

low for one cycle of the internal bus clock.

See section on Core Timer for detail on COP watchdog timeout periods.

5.3.4 Low Voltage Reset (LVR)

The LVR activates the RST reset signal to reset the device when the voltage on

the VDD pin falls below the LVR trip voltage. The LVR will assert the pulldown

device to pull the RESET pin low one cycle of the internal bus clock. The Low Volt-

age Reset circuit is enabled by a mask option.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

COPR

00000000

$1FF0

COPC

reset:

UUUUUUU

U = UNAFFECTED BY RESET

Figure 5-2. COP Watchdog Register (COPR)

Freescale Semiconductor, Inc.

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