AT25QF641 datasheet(17/74 Pages) DIALOG

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AT25QF641

DS-25QF641–127E–3/2018

IO3 = A23, A19, A15, A11, A7, A3, M7, M3

IO3 = x, x, x, x, x, x, x

Quad Input/ Output Data

IO0 = (D4, D0T)

IO1 = (D5, D1T)

IO2 = (D6, D2T)

IO3 = (D7, D3T)

Fast Read Quad I/O Data Output

IO0 = (x, x, x, x, D4, D0T)

IO1 = (x, x, x, x, D5, D1T)

IO2 = (x, x, x, x, D6, D2T)

IO3 = (x, x, x, x, D7, D3T)

10.

SC = security register

7.2

Write Enable (06h)

Write Enable instruction is for setting the Write Enable Latch (WEL) bit in the Status Register. The WEL bit must be set prior to

every Program, Erase and Write Status Register instruction. To enter the Write Enable instruction, CS goes low prior to the

instruction “06h” into Data Input (SI) pin on the rising edge of SCK, and then driving CS high.

Figure 7-1.

Write Enable Instruction for SPI Mode (left) and QPI Mode (right)

7.3

Write Enable for Volatile Status Register (50h)

This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting

for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. To write the

volatile values into the Status Register bits, the Write Enable for Volatile Status Register (50h) instruction must be issued

prior to a Write Status Register (01h) instruction. Write Enable for Volatile Status Register instruction (Figure 7-2) will

not set the Write Enable Latch (WEL) bit. Once Write Enable for Volatile Status Register is set, a Write Enable

instruction should not have been issued prior to setting Write Status Register instruction (01h or 31h).

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