MPC7445 datasheet(15/56 Pages) NXP

15 / 56 page

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

Electrical and Thermal Characteristics

Figure 3 provides the SYSCLK input timing diagram.

Figure 3. SYSCLK Input Timing Diagram

Table 8. Clock AC Timing Specifications

At recommended operating conditions. See Table 4.

Characteristic

Symbol

Maximum Processor Core Frequency

Unit Notes

1000 MHz

1267 MHz

1333 MHz

1420 MHz

Min

Max

Min

Max

Min

Max

Min

Max

Processor core frequency

fcore

600

1000

600

1267

600

1333

600

1420

MHz 1, 8, 9

VCO frequency

fVCO

1200

2000

1200

2533

1200

2667

1200

2840

MHz

1, 9

SYSCLK frequency

fSYSCLK

167

MHz 1, 2, 8

SYSCLK cycle time

tSYSCLK

6.0

SYSCLK rise and fall time

tKR, tKF

—1.0

—

1.0

—

1.0

SYSCLK duty cycle measured at

OVDD/2

tKHKL/

tSYSCLK

SYSCLK cycle-to-cycle jitter

—

150

—

150

—

150

—

150

5, 6

Internal PLL relock time

—

100

—

100

—

100

—

100

μs7

Notes:

1. Caution: The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus)

frequency, processor core frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum

operating frequencies. Refer to the PLL_CFG[0:4] signal description in Section 9.1.1, “PLL Configuration,” for valid

PLL_CFG[0:4] settings.

2. Assumes a lightly-loaded, single-processor system.

3. Rise and fall times for the SYSCLK input measured from 0.4 to 1.4 V.

4. Timing is guaranteed by design and characterization.

5. Guaranteed by design.

6. The SYSCLK driver’s closed loop jitter bandwidth should be less than 1.5 MHz at –3 dB.

7. Relock timing is guaranteed by design and characterization. PLL relock time is the maximum amount of time required

for PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also

applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET

must be held asserted for a minimum of 255 bus clocks after the PLL relock time during the power-on reset sequence.

8. Caution: If DFS is enabled, the SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the

resulting processor frequency is greater than or equal to the minimum core frequency.

9. Caution: These values specify the maximum processor core and VCO frequencies when the device is operated at

the nominal core voltage. If operating the device at the derated core voltage, the processor core and VCO frequencies

must be reduced. See Section 5.3, “Voltage and Frequency Derating,” for more information.

SYSCLK

CVIH

CVIL

VM = Midpoint Voltage (OVDD/2)

tSYSCLK

tKR

tKF

tKHKL

MPC7445 Datasheet(PDF) 15 Page - NXP Semiconductors

MPC7445 Datasheet(HTML) 15 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datasheet Download

Link URL