MPC7445 datasheet(38/56 Pages) NXP

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MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

System Design Information

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic surface mount technology (SMT)

capacitors should be used to minimize lead inductance. Orientations where connections are made along

the length of the part, such as 0204, are preferable but not mandatory. Consistent with the

recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic

(Prentice Hall, 1993) and contrary to previous recommendations for decoupling Freescale

microprocessors, multiple small capacitors of equal value are recommended over using multiple values of

capacitance.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,

feeding the VDD and OVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk

capacitors should have a low equivalent series resistance (ESR) rating to ensure the quick response time

necessary. They should also be connected to the power and ground planes through two vias to minimize

inductance. Suggested bulk capacitors are: 100–330 µF (AVX TPS tantalum or Sanyo OSCON).

9.4

Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal

level. Unless otherwise noted, unused active-low inputs should be tied to OVDD, and unused active-high

inputs should be connected to GND. All NC (no connect) signals must remain unconnected.

Power and ground connections must be made to all external VDD, OVDD, and GND pins in the

MPC7447A. For backward compatibility with the MPC7447, MPC7445, and MP7441, or for migrating a

system originally designed for one of these devices to the MPC7447A, the new power and ground signals

(formerly NC, see Table 12) may be left unconnected. There is no performance degradation associated

with leaving these pins unconnected. However, future devices may require these additional power and

ground signals to be connected to achieve maximum performance, and it is recommended that new designs

include the additional connections to facilitate future upgrades. See also Section 7, “Pinout Listings,” for

additional information.

9.5

Output Buffer DC Impedance

The MPC7447A processor bus drivers are characterized over process, voltage, and temperature. To

measure Z0, an external resistor is connected from the chip pad to OVDD or GND. The value of each

resistor is varied until the pad voltage is OVDD/2. Figure 18 shows the driver impedance measurement.

The output impedance is the average of two components—the resistances of the pull-up and pull-down

devices. When data is held low, SW2 is closed (SW1 is open), and RN is trimmed until the voltage at the

pad equals OVDD/2. RN then becomes the resistance of the pull-down devices. When data is held high,

SW1 is closed (SW2 is open), and RP is trimmed until the voltage at the pad equals OVDD/2. RP then

becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in value.

Then, Z0 = (RP + RN)/2.

MPC7445 Datasheet(PDF) 38 Page - NXP Semiconductors