AT90USB646 datasheet(265/434 Pages) ATMEL

265 / 434 page

265

7593A–AVR–02/06

AT90USB64/128

DPADD10:8 is the most significant part of DPADD. The least significant part is provided by the

UDPADDL register.

• 7-0 – DPADD7:0: DPRAM Address Low Bit

DAPDD7:0 is the least significant part of DPADD. The most significant part is provided by the

UDPADDH register.

• 7-6 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 5 – HNPREQ: HNP Request Bit

Set to initiate the HNP when the controller is in the Device mode (B). Set to accept the HNP

when the controller is in the Host mode (A).

Clear otherwise.

• 4 – SRPREQ: SRP Request Bit

Set to initiate the SRP when the controller is in Device mode. Cleared by hardware when the

controller is initiating a SRP.

• 3 – SRPSEL: SRP Selection Bit

Set to choose VBUS pulsing as SRP method.

Clear to choose data line pulsing as SRP method.

• 2 – VBUSHWC: VBus Hardware Control Bit

Set to disable the hardware control over the UVCON pin.

Clear to enable the hardware control over the UVCON pin.

See for more details

• 1 – VBUSREQ: VBUS Request Bit

Set to assert the UVCON pin in order to enable the VBUS power supply generation. This bit

shall be used when the controller is in the Host mode.

Cleared by hardware when VBUSRQC is set.

• 0 – VBUSRQC: VBUS Request Clear Bit

Bit

765

4321

DPADD7:0

UDPADDL

Read/Write

Initial Value

000

0000

Bit

HNPREQ

SRPREQ

SRPSEL

VBUSHWC

VBUSREQ

VBUSRQC

OTGCON

Read/Write

R/W

Initial Value

AT90USB646 Datasheet(PDF) 265 Page - ATMEL Corporation

AT90USB646 Datasheet(HTML) 265 Page - ATMEL Corporation

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