12-Bit DACs with 32-Channel

Sample-and-Hold Outputs

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9

Detailed Description

Sample-and-Hold Amplifiers

The MAX5331/MAX5332/MAX5333 contain 32 buffered

SHA circuits with internal hold capacitors. Internal hold

capacitors minimize leakage current, dielectric absorp-

tion, feedthrough, and required board space. The

MAX5331/MAX5332/MAX5333 provide a very low

1µV/ms droop rate.

Output

The MAX5331/MAX5332/MAX5333 include output buffers

on each channel. The devices contain output resistors in

series with the buffer output (Figure 3) for ease of output

filtering and capacitive load driving stability.

increases power dissipation. Do not exceed the maxi-

mum power dissipation specified in the Absolute

Maximum Ratings.

The maximum output voltage range depends on the

analog supply voltages available and the output clamp

voltages (see the Output Clamp section):

The devices have a fixed theoretical output range

determined by the reference voltage, gain, and mid-

scale offset. The output voltage for a given input code

is calculated as follows:

where code is the decimal value of the DAC input

voltage at the ground-sense input. With a 2.5V refer-

ence, the nominal end points are -4.0535V and

+9.0503V (Table 1). Note that these are “virtual” internal

end-point voltages and cannot be reached with all

V

code

V

VV

OUT

REF

REF

GS

_

.

= 







××

×

4096

5 2428

1 6214

-

.

VV

V

V

V

SS

OUT

DD

+

075

2 4

..

_

-

Table 1. Code Table

DAC INPUT CODE

MSB

LSB

NOMINAL OUTPUT

VOLTAGE (V)

1111 1111 1111

9.0503

Full-scale output.

1100 0111 0101

6.15

1000 0000 0000

2.5

Midscale output.

0100 1111 0011

0

0010 1000 0010

-2.0

0000 0000 0000

-4.0535

Zero-scale output.

CS

SCLK

DIN

B23

B22

B0

Figure 2. Serial-Interface Timing Diagram