12-Bit DACs with 32-Channel

Sample-and-Hold Outputs

10

______________________________________________________________________________________

combinations of negative and positive power-supply

voltages. The nominal, usable DAC end-point codes for

the selected power supplies can be calculated as:

3.2mV) (result

≥ 0)

3.2mV) (result

≤ 4095)

The resistive voltage-divider formed by the output resis-

Ground Sense

The MAX5331/MAX5332/MAX5333 include a ground-

sense input (GS), which allows the output voltages to

be referenced to a remote ground. The voltage at GS is

added to the output voltage with unity gain. Note that

the resulting output voltage must be within the valid

output voltage range set by the power supplies.

Output Clamp

The MAX5331/MAX5332/MAX5333 clamp the output

between two externally applied voltages. Internal

diodes at each channel restrict the output voltage to:

The clamping diodes allow the MAX5331/MAX5332/

MAX5333 to drive devices with restricted input ranges.

The diodes also allow the outputs to be clamped during

power-up or fault conditions. To disable output clamping,

voltages beyond the maximum output voltage range.

Serial Interface

The MAX5331/MAX5332/MAX5333 are controlled by an

SPI-/QSPI-/MICROWIRE-compatible 3-wire interface.

Serial data is clocked into the 24-bit shift register in an

MSB-first format, with the 12-bit DAC data and S3–S0

(all zeros) preceding the 5-bit SRAM address, 2-bit

control, and a fill zero (Figure 4). The input word is

framed by CS. The first rising edge of SCLK after CS

goes low clocks in the MSB of the input word.

VV

V

V

V

CH

OUT

CL

.

.

_

+

−

07

07

Scaling factor

R

RR

VV

scaling factor

L

LO

OUT

CHOLD

=

+

=×

_

DATA

ADDRESS

CONTROL

D11 D10

D9

D8

D7D6

D5D4

D3D2

D1D0

S3

S2

S1

S0

A4

A3

A2

A1

A0

C1

C0

0

0

000

0

MSB

LSB

Figure 4. Input-Word Sequence

Figure 3. Analog Block Diagram

GS

DAC

DATA

CH

OUT_

GAIN

AND

OFFSET

ONE OF 32 SHA CHANNELS

12-BIT

DAC

CL