LTC4282 datasheet(12/82 Pages) AD

12 / 82 page

LTC4284

Rev. B

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PIN FUNCTIONS

ADC+ (Pin 16): Positive Current Sense Kelvin Input to

ADC. Connect to the tap of an external resistive divider

between SENSE1+ and SENSE2+ to measure the average

between those two pins. Connect to SENSE1+ when using

a single sense resistor. Connect to VEE if unused.

ADC− (Pin 13): Negative Current Sense Kelvin Input to

ADC. Connect to the tap of an external resistive divider

between SENSE1− and SENSE2− to measure the average

between those two pins. Connect to SENSE1− when using

a single sense resistor. Connect to VEE if unused.

ADIN1–ADIN4 (Pins 7–10): ADC Inputs. A single-ended

voltage between 0V and 2.048V applied to each ADIN

is measured by the on-chip ADC. Two differential volt-

ages ADIN2 – ADIN1 and ADIN4 – ADIN3, if enabled, are

also measured by the ADC with a full scale of 32.768mV.

Connect to VEE if unused.

ADIO1–ADIO4 (Pins 25–28): General Purpose Inputs/

Outputs and ADC Inputs. Configurable to logic inputs

and general purpose outputs (open-drain). See Table 13

for details. The single-ended voltages at ADIOs are mea-

sured by the ADC with a full scale of 2.048V. The dif-

ferential voltages ADIO2 – ADIO1 and ADIO4 – ADIO3, if

enabled, are also measured by the ADC with a full scale

of 32.768mV. Connect to VEE if unused.

ADR0, ADR1 (Pin 38, Pin 39): Serial Bus Address Inputs.

Connecting to VEE, OPEN or INTVCC configures one of nine

possible addresses, with one dedicated to the single-wire

broadcast mode. Do not bias with an external supply. See

Table 2 in Applications Information for address decoding.

ALERT# (Pin 34): Fault Alert Output. Open-drain logic

output that pulls to VEE when a fault occurs to alert the

host controller. A fault alert is enabled by the FAULT_

ALERT and ADC_ALERT registers. See Tables 15 and 16

in Applications Information for details. Connect to VEE if

unused.

DRAIN (Pin 20): Drain Sense Input. Connect an external

100k resistor between this pin and the drain terminal of

the N-channel MOSFET. A DRAIN voltage below 2.048V is

one of the conditions to assert power good outputs and

turn on GATE2 in the high stress staged start (Mode 3)

or low stress staged start mode (Mode 4). When DRAIN

voltage is above a voltage configurable between 72mV

and 203mV, the FET Bad fault timer is started and the

TMR output current is enabled when not in current limit.

DRAIN is internally clamped to a minimum of 3.2V.

INPUT = VRTNS

REJECTION LIMITED BY

QUANTIZATION NOISE

FREQUENCY (kHz)

100

150

200

–80

–60

–40

–20

4284 G25

300 UNITS

260°C 3 CYCLES

INPUT = VADIN1

FSE SHIFT (%)

–0.3 –0.2 –0.1 0.0 0.1 0.2 0.3 0.4 0.5

100

4284 G26

300 UNITS

260°C 3 CYCLES

VILIM SHIFT (%)

–1.2

–0.8

–0.4

0.0

0.4

0.8

1.2

4284 G27

100

TYPICAL PERFORMANCE CHARACTERISTICS

12-Bit ADC Input Signal Attenuation

(Extended Frequencies)

ADC FSE Shift Due to IR Reflow

VILIM Shift Due to IR Reflow

LTC4282 Datasheet(PDF) 12 Page - Analog Devices

LTC4282 Datasheet(HTML) 12 Page - Analog Devices

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