LTC4282 datasheet(28/82 Pages) AD

28 / 82 page

LTC4284

Rev. B

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APPLICATIONS INFORMATION

After the internal power good signal is latched (see Power

Good Monitors and PGI Fault), the LTC4284 goes into

normal operation and the foldback is determined by the

attenuated output voltage for the load, RTNS – DRNS

(Figure 8b). If the output voltage or RTNS – DRNS drops

to 0V in an event such as a catastrophic output short, the

current limit sense voltage is folded back to the ratio con-

figured by the FB bits. As shown in Figure 8b, the foldback

ratio increases linearly with RTNS – DRNS and reaches

100% when RTNS – DRNS reaches 0.9V, which corre-

sponds to the minimum supply voltage of an application.

Above 0.9V the current limit sense voltage stays constant

unless the load power foldback (LPFB) bit in the CONFIG_1

Figure 8a. Current Limit Foldback During Startup

Figure 8b. Current Limit Foldback in Normal Operation

limit sense voltage decreases linearly to 50% when RTNS

– DRNS reaches 1.8V (corresponding to the maximum

supply voltage). This profile approximately tracks the load

power when the output voltage increases with a constant

power load.

The LTC4284 foldback profile can differentiate an output

short fault from an allowed input step. Upon an output

short, RTNS – DRNS drops and current limit is folded back

to protect the MOSFETs from overstress. In the event of

an input step, RTNS – DRNS increases while the load is

charged up. The current limit either stays constant or

approximates constant load power (based on the LPFB

bit) to approach the optimum output ramp and minimize

the temperature rise of the MOSFETs (see Input Step and

Optimum Output Ramp). This is superior to a foldback

profile capacitance based upon VDS or power dissipation

of the MOSFET. In that case, the output short and input

step conditions cannot be differentiated, often resulting

in unwanted turn-off upon an input step.

Foldback in normal operation can be independently dis-

abled by setting the FB_DIS bit in the CONFIG_1 register

0x0D. With this configuration foldback is only effective

during startup, and it should only be used when an RC

network representing the thermal model of the MOSFET

is connected to TMR. If a single capacitor is used, it is

recommended to enable foldback in normal operation by

clearing the FB_DIS bit for more conservative protection

of the MOSFET. Note that the load power foldback con-

trolled by the LPFB bit is not affected by the FB_DIS bit.

FET Bad Fault and Auto-Retry

In a hot swap application several possible faults can

prevent the MOSFETs from turning on fully. A damaged

MOSFET may have leakage from gate to drain or have

degraded RDS(ON). Debris on the board may also pro-

duce leakage or a short from the GATE pins to VEE or the

MOSFET drain. In these conditions the LTC4284 may not

be able to pull the GATE pins high enough to fully enhance

the MOSFETs, or the MOSFETs may not reach the intended

RDS(ON) when the GATE pins are fully enhanced. This can

put the MOSFETs in a condition where the power in the

MOSFETs is higher than its continuous power capability,

even though the current is below the current limit. The

VRTNS – VDRNS (V)

VRTNS = 1.8V

100

0.9

4284 F08a

1.8

FB = 11

FB = 10

FB = 01

FB = 00

VRTNS – VDRNS (V)

100

0.9

4284 F08b

1.8

LPFB = 0

LPFB = 1

FB = 00

VRTNS = 1.8V

LTC4282 Datasheet(PDF) 28 Page - Analog Devices

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