LTC4282 datasheet(17/82 Pages) AD

17 / 82 page

LTC4284

Rev. B

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OPERATION

The LTC4284 is designed to turn a board’s supply voltage

on and off in a controlled manner, allowing the board to be

safely inserted or removed from a live, high power sys-

tem. The device features four distinct operation modes:

single driver mode (Mode 1), parallel mode (Mode 2), high

stress staged start mode (Mode 3), and low stress staged

start mode (Mode 4). Each of these modes addresses

specific application requirements for SOA (Safe Operating

Area), RDS(ON), and cost.

In normal operation after a startup debounce delay, the

LTC4284 turns on the external N-channel MOSFETs,

passing the power to the load. The inrush control dur-

ing startup is configurable between two methods. One is

programmable active current limiting with an adjustable

foldback factor. The other is constant dV/dt ramp control

of the output voltage using a capacitor connected between

RAMP and VEE. The inrush current is a function of the

RAMP capacitor, the load capacitor and the attenuated

load voltage seen between RTNS and DRNS.

An 11.5V shunt regulator on VIN powers the LTC4284

with an external dropping resistor from the system RTN

node. It also provides gate drive for GATE1 and GATE2.

An optional buffer transistor driven by VZ boosts sourcing

capability to supply external loads.

An internally generated 5V supply on INTVCC supplies the

logic control circuits, communication interface, data con-

verters and EEPROM. Prior to turning on the MOSFETs,

both VIN and INTVCC voltages must exceed their under-

voltage lockout thresholds. In addition, the control inputs

UVH, UVL, OV, EN#, PGIO3 and PGIO4 are monitored by

comparators. The MOSFETs are held off until all startup

conditions are met.

The DRAIN, RTNS − DRNS and GATE voltages are moni-

tored to determine if power is available for the load. Two

power good signals are sequenced on PGIO1 and PGIO2,

each with a delay that is twice the startup debounce delay.

Additionally, PGIO3 serves as a watchdog input to monitor

the output of the DC/DC module. If the module output fails

to come up, the LTC4284 turns off the MOSFETs. PGIO4

defaults as an external fault input (inverted). PGIO1-4 can

also be configured into general purpose inputs or outputs.

An overcurrent fault at the output may result in exces-

sive MOSFET power dissipation during Active Current

Limiting (ACL). To limit this power in each channel, the

ACL amplifiers regulate the SENSE1+ – SENSE1− and

SENSE2+ – SENSE2− voltages at precise, programmable

values (15mV to 30mV in 1mV steps). When the output

voltage is low, power dissipation is further reduced by

folding back the current limit, with the foldback ratio con-

figurable to 10%, 20%, or 50% of nominal. In the event

of a catastrophic output short when the sensed current

is twice of the current limit, fast response comparators

immediately pull the GATE pins down with 1.2A.

When active current limiting is engaged, TMR is pulled

up by a current that is proportional to the power dissipa-

tion in the MOSFET (M1) driven by GATE1. With an RC

network representing the thermal behavior of M1 con-

nected between TMR and VEE, the TMR voltage is propor-

tional to the temperature rise in M1. When TMR voltage

reaches its threshold of 2.048V (representing TJ(MAX) of

the MOSFET), the overcurrent fault is logged and both

GATE1 and GATE2 turn off, allowing protection of the

MOSFETs based on true SOA. TMR can also be config-

ured to drive a single capacitor. Following the overcurrent

fault, the LTC4284 can either latch off the MOSFETs or

auto-retry after a cooling delay. Both the retry delay and

the number of retries are configurable, too. The LTC4284

also logs and responds to other faults including overvolt-

age, undervoltage, FET bad, Power Good Input (PGI) fault,

FET short and external fault.

Included in the LTC4284 is a pair of analog to digital con-

verters (ADCs). The ADCs are configurable from 8-bit at

1kHz to 16-bit at 1Hz in five settings. As shown in the

Block Diagram, ADC1 continuously monitors the current

sense voltage between ADC+ and ADC−. ADC2 is syn-

chronized to ADC1 and measures the attenuated input

voltage at RTNS or the attenuated MOSFET drain voltage

at DRNS plus one of the sixteen auxiliary inputs. Every

time the ADCs finish taking a measurement, the current

sense voltage is multiplied by the measurement of the

RTNS or DRNS voltage to provide a power measurement.

Every time power is measured, it is added to an energy

accumulator that tracks the input energy or the energy

consumption of the MOSFET. The energy accumulator

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