LTC4282 datasheet(23/82 Pages) AD

23 / 82 page

LTC4284

Rev. B

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APPLICATIONS INFORMATION

and regulates the inrush current to a fixed value that is a

function of the attenuation ratio, r and the ratio between

load capacitance and RAMP capacitance:

IINRUSH = 2.5µA •r •

The attenuation ratio r is set by the external resistive divid-

ers at RTNS (RRT and RRB) and DRNS (RDT and RDB) in

Figure 6:

RRT+RRB

RRB

RDT+RDB

RDB

RTNS and DRNS represent the attenuated input voltage

and MOSFET drain voltage, respectively. The differential

voltage between RTNS and DRNS therefore represents

the attenuated load voltage. The operation range of VRTNS,

VDRNS and VRTNS – VDRNS is from 0V to 2.8V.

The dV/dt control is only active during initial startup.

After the turn-on sequence is completed and power good

signals are activated, the dV/dt inrush control mode is

disabled and RAMP is discharged with a 4mA current.

RAMP will also be discharged under any GATE turn-off

conditions. In the dV/dt mode the inrush current must be

set lower than the folded back current limit level to avoid

triggering the current limit (see below).

The second inrush control mechanism is active cur-

rent limiting. This is enabled by clearing the DVDT bit in

CONTROL_1 register 0x0A. In this mode the inrush cur-

rent is regulated to the folded back current limit:

IINRUSH = ILIM • aSTARTUP

where ILIM is the current limit and aSTARTUP is the startup

foldback factor. ILIM is determined by the current limit

sense voltage VILIM and the sense resistance RS.

ILIM=

VILIM

VILIM is configurable from 15mV to 30mV in 1mV steps.

aSTARTUP is configurable to 10%, 20%, 50% and 100%

(no foldback) of current limit. During startup the current

limit foldback profile is flat and does not change with

output voltage. See Current Limit Adjustment and Current

Limit Foldback for details. In this mode the RAMP capaci-

tor CR at the RAMP pin no longer takes effect. If CR is

omitted, RAMP must be left open.

In parallel mode or single driver mode, GATE1 and GATE2

are turned on simultaneously to charge the load capacitor.

In staged start modes, GATE1 is turned on first to charge

the load capacitor and GATE2 is turned on after the load

capacitor is fully charged. See High Stress Staged Start

Mode (Mode 3) and Low Stress Staged Start (Mode 4)

for details.

Power Good Monitors and PGI Fault

After the MOSFETs are turned on, the following conditions

must be met before the power good signals are activated.

First, the DRAIN voltage must fall below 2.048V to indicate

the MOSFET drain is low. Second, RTNS − DRNS must be

higher than the external threshold voltage at VOUTTH to

indicate the output voltage is high. Last, GATE voltages

must satisfy the GATE high (>VIN – 1.8V) condition. For

parallel mode, one GATE must be high and the other GATE

must be either high or in current limit. When all three condi-

tions are met, an internal power good signal is latched, the

PG_STATUS bit in SYSTEM_STATUS register 0x00 is set,

and a series of three delay cycles are started as illustrated

in Figure 5. When the first delay of 256ms expires, the first

power good signal PGIO1 turns on the first load. When the

second delay of 256ms expires, the second power good

signal PGIO2 can be used to turn on a second load.

Following the two 256ms delays, a third delay of 512ms is

started for monitoring PGIO3 as a power good input (PGI)

watchdog. Before this delay expires, PGIO3 must be pulled

low or high (polarity configurable by register 0x10) by an

external supply monitor to indicate the load is working prop-

erly. Otherwise, the MOSFETs are turned off and a PGI fault

is logged in FAULT register 0x04. The MOSFETs are allowed

to auto-retry after a delay of 128ms following the PGI fault

if the PGI_RETRY bit in CONTROL_2 register 0x0B is set

to 1. Both power good signals and the power good input

can be configured into inverted or non-inverted polarity

using PGIO_CONFIG_1 register 0x10 (see Table 12). To

disable the PGI watchdog, connect PGIO3 to VEE or INTVCC

depending on the configured polarity, or configure PGIO3

as general purpose input or output using register 0x10.

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