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ML54053

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3. PIN SPECIFICATIONS

Refer to Section 11, “Application Example” for specific connection examples.

3.1 Host Interface

Signal Name

ha [10:0]

hd [15:0]

hcen [2:1]

hiordn

hiowrn

hoen

hwen

hregn

hirqn

hstschgn

hinpackn

Type

Pin Count

Description

Address bus (A10 is MSB, A0 is LSB)

Data bus (D15 is MSB, D0 is LSB)

Card enable signal (hcen1 controls even addresses and hcen2 controls odd

addresses. The combination of ha0, hcen1 and hcen2 allows even/odd

addresses to be accessed by hd[7:0].)

I/O read signal (control signal to read data from ATA registers)

I/O write signal (control signal to write data to ATA registers)

Output enable signal

Write enable signal

Interrupt request signal (when the card is configured as an I/O card)

Card status change signal (signal to change the status of the configuration

status register)

Input port acknowledge signal (acknowledge signal during I/O read)

hiois16n

16-bit address enable signal (when the card is configured as an I/O card,

this signal indicates that 16-bit addresses are enabled)

hwaitn

Wait signal

hspkr

Audio digital waveform signal

hrst

Reset signal

hcseln

Cable select signal (used only in True IDE Mode, GND: Master, X: Slave)

Total 42 pins

I: Input, O: Output, B: Bidirectional

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