¡ Semiconductor

ML54053

4/22

3.2 NAND Flash Memory Interface

Signal Name

maio [7:0]

macle

maale

maren

mawen

marbn

mbio [7:0]

mbcle

mbale

mbren

mbwen

Type

B

O

O

O

O

I

B

O

O

O

O

Pin Count

8

1

1

1

1

1

8

1

1

1

1

Description

Port A I/O bus

Port A command latch enable signal (signal to control latching of an

operation command into a device)

Port A address latch enable signal (signal to control latching of an address

or input data into a device)

Port A read enable signal

Port A write enable signal (signal to latch data into a device)

Port A ready/busy signal (signal to check internal status of device)

Port B I/O bus

Port B command latch enable signal (signal to control latching of an

operation command into a device)

Port B address latch enable signal (signal to control latching of an address

or input data into a device)

Port B read enable signal

Port B write enable signal (signal to latch data into a device)

mbrbn

I

1

Port B ready/busy signal (signal to check internal status of device)

mcen [3:0]

O

4

Chip enable signals

Total 31 pins

mwpn

O

1

Write protect signal (signal to forcibly prohibit write and erase operations)

3.3 Extended Bus Interface

The extended bus interface is a signal line for the ML54053’s internal microcontroller. The

extended bus interface is used for purposes such as debugging.

*

In an external ROM connection mode, xah, xad, xrd, xwr, and xale are used to connect to

external ROM.

Signal Name

xah [15:8]

Type

B

Pin Count

8

Description

Address bus for extended bus

Total 23 pins

xad [7:0]

B

8

Address/data bus for extended bus

xrd

B

1

Read signal for extended bus

xwr

B

1

Write signal for extended bus

xale

B

1

Address latch enable signal for extended bus

xpsen

I

1

Program store enable signal for extended bus

xint

O

1

Interrupt signal for extended bus

xrst

O

1

Reset signal for extended bus

xclk

O

1

Clock signal for extended bus