¡ Semiconductor

ML54053

5/22

*

The chip mode is determined depending upon the status of pcfg[1:0] when the porn signal

rises.

pcfg[1:0] = 11 : Normal mode

pcfg[1:0] = 01 : External CPU connection mode

pcfg[1:0] = 10 : External ROM connection mode

pcfg[1:0] = 00 : Test mode (normally not used)

3.4 Other Interfaces

Signal Name

txd/pcfg [0]

Type

B

Pin Count

1

Description

Serial data I/O and chip mode setting

Total 5 pins

rxd/pcfg [1]

I

1

porn

I

1

Power-on-reset signal (connect to power monitor circuit)

xin

I

1

Clock I/O (connect a crystal oscillator between xin and xout)

xout

O

1

3.5 Power Supply

3.6 Pin Totals

Signal Name

VDD-CORE

Type

DC

Pin Count

2

Description

Power supply for core

Total 19 pins

VSS-CORE

DC

2

VDD

DC

6

Power supply for I/O pad

VSS

DC

9

NAND Flash Memory Interface

31

Host Interface

42

Extended Bus Interface

23

Other Interfaces

5

Power Supply

19

Total

120