6.7 Timing Requirements (continued)

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.

MIN

NOM

MAX

UNIT

ENABLE+REFGEN

Power-up receiver(4)

2000

ns

(1)

Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in Figure 6-3.

(2)

Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 6-3.

(3)

Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns.

(4)

Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.

LS_ WDATA

LS_CLK

50%

50%

50%

50%

50%

Low-speed interface is LPSDR and adheres to the Section 6.6 and AC/DC Operating Conditions table in JEDEC Standard No. 209B,

Low Power Double Data Rate (LPDDR) JESD209B.

Figure 6-2. LPSDR Switching Parameters

0.0 * VDD

0.2 * VDD

0.3 * VDD

0.7 * VDD

0.8 * VDD

1.0 * VDD

LS_CLK, LS_WDATA

0.0 * VDD

0.2 * VDD

0.8 * VDD

1.0 * VDD

DMD_DEN_ARSTZ

Figure 6-3. LPSDR Input Rise and Fall Slew Rate

DLP160AP

DLPS226 – OCTOBER 2021

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