DLP160AP datasheet(3/41 Pages) TI

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5 Pin Configuration and Functions

Figure 5-1. FQT Package 35-Pin

Table 5-1. Connector Pins

PIN(1)

PACKAGE NET

LENGTH (mm)(2)

NAME

NO.

TYPE

SIGNAL

DATA RATE

DESCRIPTION

DATA INPUTS

D_N(0)

SubLVDS

Double

Data, negative

1.91

D_N(1)

SubLVDS

Double

Data, negative

3.6

D_N(2)

SubLVDS

Double

Data, negative

3.28

D_N(3)

SubLVDS

Double

Data, negative

1.67

D_P(0)

SubLVDS

Double

Data, positive

2.03

D_P(1)

SubLVDS

Double

Data, positive

3.7

D_P(2)

SubLVDS

Double

Data, positive

3.39

D_P(3)

SubLVDS

Double

Data, positive

1.77

DCLK_N

SubLVDS

Double

Clock, negative

2.29

DCLK_P

SubLVDS

Double

Clock, positive

2.4

CONTROL INPUTS

LS_WDATA

C12

LPSDR

Single

Write data for low-

speed interface

1.55

LS_CLK

C13

LPSDR

Single

Clock for low-

speed interface

1.65

DMD_DEN_ARST

D12

LPSDR

Single

Asynchronous

reset DMD signal.

A low signal

places the DMD

in reset. A high

signal releases the

DMD from reset

and places it in

active mode.

1.57

LS_RDATA

D13

LPSDR

Single

1.43

POWER

VBIAS (3)

A13

Power

Supply voltage for

positive bias level

at micromirrors

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DLP160AP

DLPS226 – OCTOBER 2021

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