MM9Z1 datasheet(30/452 Pages) NXP

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NXP Semiconductors

MM9Z1_638

ELECTRICAL CHARACTERISTICS

4.6.3

Electrical specification for voltage regulator

Note

The LVR monitors the voltages VDD, VDDF, and VDDRX. As soon as voltage drops on these supplies

which would prohibit the correct function of the microcontroller, the LVR is triggering a reset.

4.6.3.1

Chip power-up and voltage drops

LVI (low voltage interrupt), POR (power-on reset) and LVRs (low voltage reset) handle chip power-up or drops of the supply voltage.

Table 41. ivregcrz_ll18 characteristics

Num

Characteristic

Symbol

Min.

Typ.

Max.

Unit

Input Voltages

VVDDRX

3.13

—

5.5

VDDRX Low Voltage Interrupt Assert Level (54)

VDDRX Low Voltage Interrupt Deassert Level

VLVIA

VLVID

4.04

4.19

4.23

4.38

4.47

4.60

PVDDRX Low Voltage Reset Deassert (55), (56)

VLVRXD

—

3.25

CPMU ACLK frequency

(CPMUACLKTR[5:0] = %000000)

fACLK

—20

—

kHz

Trimmed ACLK internal clock(57)

Δf / fNOMINAl

dfACLK

- 5.0

—

+ 5.0

The first period after enabling the counter by APIFE might be

reduced by ACLK start up delay

tsdel

—

100

The first period after enabling the COP might be reduced by

ACLK start up delay

tSDEL

—

100

VDDRX Low Voltage Reset(58)

Assert Level

Deassert Level

VLVRXA

VLVRXD

2.906

—

3.037

3.054

—

3.25

Notes:

54.Monitors VDDA, active only in Full Performance mode. Indicates I/O & ADC performance degradation due to low supply voltage.

55.Device functionality is guaranteed on power down to the LVR assert level

56.Monitors VDDRX, active only in Full Performance mode. MCU is monitored by the POR in RPM (see Figure 7)

57.The ACLK Trimming CPMUACLKTR[5:0] bits must be set so that fACLK=10KHz.

58.Monitors VDDRX, active only in Full Performance mode. VLVRA and VPORD must overlap (see Figure 7)

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