MM9Z1 datasheet(32/452 Pages) NXP

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NXP Semiconductors

MM9Z1_638

ELECTRICAL CHARACTERISTICS

4.6.5

PLL electrical specifications

4.6.5.1

Reset, oscillator and PLL

4.6.5.2

Phase locked loop

4.6.5.2.1

Jitter information

With each transition of the feedback clock, the deviation from the reference clock is measured and the input voltage to the VCO is adjusted

accordingly.The adjustment is done continuously with no abrupt changes in the VCOCLK frequency. Noise, voltage, temperature and other

factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods

as illustrated in Figure 8.

N-1

tNOM

tMAX1

tMIN1

tMAXN

tMINN

Figure 8. Jitter definitions

The relative deviation of tNOM is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N).

Defining the jitter as:

()

max 1

tmax N

()

Ntnom

⋅

-----------------------

–

tmin N

()

Ntnom

⋅

-----------------------

–







The following equation is a good fit for the maximum jitter:

()

--------

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