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MM9Z1 Datasheet(PDF) 84 Page - NXP Semiconductors |
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MM9Z1 Datasheet(HTML) 84 Page - NXP Semiconductors |
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84 / 452 page ![]() 84 NXP Semiconductors MM9Z1_638 FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION 6.2.1.6.2.6 S12ZCPMU interrupt enable register (CPMUINT) This register enables S12ZCPMU interrupt requests. 6.2.1.6.2.7 S12ZCPMU clock select register (CPMUCLKS) This register controls S12ZCPMU clock selection. Table 72. S12ZCPMU interrupt enable register (CPMUINT) Module base + 0x0008 765 4321 0 R RTIE 00 LOCKIE 00 OSCIE 0 W Reset 000 0000 0 = Unimplemented or Reserved Notes: 84.Read: Anytime Write: Anytime Table 73. CPMUINT field descriptions Field Description 7 RTIE Real Time Interrupt Enable Bit 0 Interrupt requests from RTI are disabled. 1 Interrupt will be requested whenever RTIF is set. 4 LOCKIE PLL Lock Interrupt Enable Bit 0 PLL LOCK interrupt requests are disabled. 1 Interrupt will be requested whenever LOCKIF is set. 1 OSCIE Oscillator Corrupt Interrupt Enable Bit 0 Oscillator Corrupt interrupt requests are disabled. 1 Interrupt will be requested whenever OSCIF is set. Table 74. S12ZCPMU clock select register (CPMUCLKS) Module Base + 0x0009 76 54 32 1 0 R PLLSEL PSTP CSAD COP OSCSEL1 PRE PCE RTI OSCSEL COP OSCSEL0 W Reset 1 00 00 000 = Unimplemented or Reserved Notes: 85.Read: Anytime Write: Anytime • Only possible if PROT=0 (CPMUPROT register) in all MCU Modes (Normal and Special mode). • All bits in Special mode (if PROT=0). • PLLSEL, PSTP, PRE, PCE, RTIOSCSEL: In Normal mode (if PROT=0). • CSAD: In Normal mode (if PROT=0) until CPMUCOP write once has taken place. • COPOSCSEL0: In Normal mode (if PROT=0) until CPMUCOP write once has taken place. If COPOSCSEL0 was cleared by UPOSC=0 (entering Full Stop mode with COPOSCSEL0=1 or insufficient OSCCLK quality), then COPOSCSEL0 can be set once again. • COPOSCSEL1: In Normal mode (if PROT=0) until CPMUCOP write once has taken place. COPOSCSEL1 will not be cleared by UPOSC=0 (entering Full Stop mode with COPOSCSEL1=1 or insufficient OSCCLK quality if OSCCLK is used as clock source for other clock domains: for instance core clock etc.). |
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