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W7100A Datasheet(PDF) 33 Page - WIZnet Co., Ltd |
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W7100A Datasheet(HTML) 33 Page - WIZnet Co., Ltd |
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33 / 160 page  W7100A Datasheet v1.2.5 33 2.4 Internal Data Memory and SFR The Figure below shows the Internal Memory and Special Function Registers (SFR) map. Figure 2.10 Internal Memory Map The lower internal RAM consists of four register banks with eight registers each, a bit- addressable segment with 128 bits (16 bytes) that begins at 0x20, and a scratchpad area with 208 bytes is embedded. With indirect addressing mode ranging from 0x80 to 0xFF, the highest 128 bytes is accessed as an internal memory. But with direct addressing mode ranging from 0x80 to 0xFF, this area is accessed as a SFR memory. Figure 2.11 SFR Memory Map New SFR – New additional SFR, described in this section Extended SFR – Extended from standard 8051, described in this section Standard – standard 8051 SFR, described in this section All of the SFR in the left hand side column ending with 0 or 8 are bit addressable. |
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