LTC3884 datasheet(12/26 Pages) AD

12 / 26 page

LTC7883

Rev. 0

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PIN FUNCTIONS

COMP[A/B][1:0]: Error Amplifier Outputs. PWM duty

cycle increases with this control voltage. These are true

low impedance outputs and cannot be directly connected

together when active. For PolyPhase operation, wiring

FB to VDD33 will three-state the error amplifier output of

that channel, making it a slave. PolyPhase control is then

implemented in part by connecting all slave COMP pins

together to one master error amplifier output.

TSNS[A/B][1:0]: External Temperature Sense Inputs. The

LTC7883 supports two methods of calculation of exter-

nal temperature based on forward-biased P/N junctions

between these pins and GND.

VINS[A/B]: VIN Supply Sense. Connect to the VIN power

supply to provide line feedforward compensation. A

change in VIN immediately modulates the input to the

PWM comparator and inversely changes the pulse width

to provide excellent transient line regulation and fixed

modulator voltage gain. An external lowpass filter can be

added to this pin to prevent noisy signals from affecting

the loop gain.

IAVGND[A/B]: IAVG Ground Reference. The same IAVGND

should be shared between all channels of a PolyPhase

rail and connected to system ground at a single point.

IAVGND may be wired directly to GND on units that do

not share phases with other units.

PG[A/B][1:0]: Power Good Indicator Open-Drain Outputs.

These outputs are driven low through a 30µs filter when

the respective channel output is below its programmed

UV fault limit or above its programmed OV fault limit.

If used, a pull-up resistor is required in the application.

Operating voltage range is GND to VDD33.

PWM[A/B][1:0]: PWM Three-State Control Outputs.

These pins provide single-wire PWM switching control

for each channel to an external gate driver, DrMOS or

power block. Operating voltage range is GND to VDD33.

SYNC[A/B]: External Clock Synchronization Input and

Open-Drain Output. If desired, an external clock can

be applied to this pin to synchronize the internal PWM

channels. If an LTC7883 unit is configured as a clock

master, this pin will also pull to ground at the selected

PWM switching frequency with a 125ns pulse width. A

pull-up resistor to 3.3V is required in the application if

SYNC is driven by any LTC7883. Minimize the capacitance

on this line to ensure its time constant is fast enough for

the application.

SCL[A/B]: Serial Bus Clock Input. A pull-up resistor to

3.3V is required in the application.

SDA[A/B]: Serial Bus Data Input and Output. A pull-up

resistor to 3.3V is required in the application.

ALERT[A/B]: Open-Drain Status Output. This pin may

be connected to the system SMBALERT wire-AND inter-

rupt signal and should be left open if not used. If used, a

pull-up resistor is required in the application. Operating

voltage range is GND to VDD33.

FLT[A/B][1:0]: Programmable Digital Inputs and Open-

Drain Outputs for Fault Sharing. Used for channel-to-chan-

nel fault communication and propagation. These pins

should be left open if not used. If used, a pull-up resistor

to 3.3V is required in the application.

RUN[A/B][1:0]: Run Control Inputs and Open-Drain

Outputs. A voltage above 2V is required on these pins

to enable the respective PWM channel. The LTC7883 will

drive these pins low under certain reset/restart conditions

regardless of any PMBus command settings. A pull-up

resistor to 3.3V is required in the application.

ASELA[1:0]: Unit A Serial Bus Address Select Pins. Connect

optional 1% resistor dividers between VDD25A and GND

to these pins to select the serial bus interface address.

ASELB[1:0]: Unit B Serial Bus Address Select Pins. Connect

optional 1% resistor dividers between VDD25B and GND

to these pins to select the serial bus interface address.

VO[A/B][1:0]CFG: Output Voltage Configuration Pins.

Connect optional 1% resistor dividers between VDD25

and GND to these pins to select the output voltage for

each channel.

FCFG[A/B]: Frequency Configuration Pins. Connect an

optional 1% resistor divider between VDD25 and GND to

these pins to configure PWM switching frequency.

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