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LTC3884 Datasheet(PDF) 17 Page - Analog Devices

Part # LTC3884
Description  Quad Output PolyPhase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management
PDF  26 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
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LTC3884 Datasheet(HTML) 17 Page - Analog Devices

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LTC7883
17
Rev. 0
For more information www.analog.com
Additional Identification Commands
The LTC7883 features a few new PMBus product identi-
fication commands as detailed in Table 2.
Switching Frequency and Phase
There is a high degree of flexibility for setting the PWM
operating frequency of the LTC7883. The switching fre-
quency of the PWM can be established with an internal
oscillator or an external time base. The internal phase-
locked loop (PLL) synchronizes PWM control to this
timing reference with proper phase relation, whether
the clock is provided internally or externally. The device
can also be configured to provide the master clock to
other ICs through PMBus command, EEPROM setting,
or external configuration resistors as outlined in appli-
cation Table 6. For PMBus or EEPROM configuration, an
LTC7883 unit is designated as a clock master by clearing
bit 4 of MFR_CONFIG_ALL_LTC3882-1. As clock master,
an LTC7883 unit will drive its open-drain SYNC pin at the
selected rate with a pulse width of 125ns. An external
pull-up resistor between SYNC and VDD33 is required in
this case. Only one unit connected to SYNC should be
designated to drive the pin. If more than one LTC7883 unit
sharing SYNC is programmed as clock master, just one
of the units is automatically elected to provide the clock.
The others disable their SYNC outputs and indicate this
with bit 10 of MFR_PADS_LTC3882-1.
OPERATION
Unlike the LTC3882-1, which only allows a fixed set of
predetermined frequencies, the LTC7883 FREQUENCY_
SWITCH command supports a continuous range of values
from 250kHz to 2.5MHz. The special case of 0x0000 for
External SYNC Only is not permitted by the LTC7883.
Sending this FREQUENCY_SWITCH command value will
result in a CML fault for invalid data.
The LTC7883 will automatically accept an external SYNC
input, disabling is own SYNC drive if necessary, as long as
the external clock frequency is greater than 1/2 of the pro-
grammed internal oscillator. Whether configured to drive
SYNC or not, an LTC7883 unit can continue PWM oper-
ation at the selected frequency (FREQUENCY_SWITCH)
using its own internal oscillator if an expected external
clock signal is not present.
The MFR_PWM_CONFIG_LTC3882-1 command can be
used to configure the phase of each channel. Desired
phase can also be set from EEPROM or external configu-
ration resistors as outlined in Table 6. Phase designates
the relationship between the falling edge of SYNC and the
internal clock edge that resets the PWM latch. That reset
turns off the top power switch, producing a PWM falling
edge. Additional small propagation delays to the PWM
control pins will apply.
Table 2. New Identification Commands
COMMAND NAME
CMD CODE
DESCRIPTION
TYPE
PAGED
DATA FORMAT
DEFAULT VALUE
UNIT A
UNIT B
ID_DEVICE_ID
0xAD
LTC7883 Model Number
R String
N
ASC
LTC7883A
LTC7883B
ID_DEVICE_REV
0xAE
LTC7883 Device Revision
Code
R String
N
ASC
C0001
C0001



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