LTC3884 datasheet(13/26 Pages) AD

13 / 26 page

LTC7883

Rev. 0

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PIN FUNCTIONS

PCFG[A/B]: Phase Configuration Pins. Connect an

optional 1% resistor divider between VDD25 and GND to

these pins to configure the phase of each PWM channel

relative to SYNC.

VDD25[A/B]: Internal 2.5V Regulator Outputs. Bypass these

pins to GND with a low ESR 1µF capacitor. Do not short

these pins together or load them with external current

beyond that required for local LTC7883 configuration.

WP[A/B]: Write Protect Inputs. If WP is above 2V, PMBus

writes are restricted and any software WRITE_PROTECT

settings for that unit are overridden. These pins have an

internal 10µA pull-up to VDD33.

SHCLK[A/B]: Share Clock Open-Drain Outputs (bussed).

Share Clock, nominally 100kHz, is used to sequence mul-

tiple rails in a power system utilizing more than one ADI

PSM controller. A pull-up resistor is required in the appli-

cation. Minimize the capacitance on this line to ensure the

time constant is fast enough for the application. Operating

voltage range is GND to VDD33.

VDD33[A/B]: Internal 3.3V Regulator Outputs. Bypass these

pins to GND with a low ESR 2.2µF capacitor. The LTC7883

may also be powered from an external 3.3V rail attached

to these pins, if also shorted to VCC[A/B]. Otherwise do not

short these pins together or overload them with external

system current. Local pull-up resistors for the LTC7883

itself may be powered from VDD33.

VCC[A/B] (Pin 25): 3.3V Regulator Input(s). Bypass these

pins, which may be shorted together, to GND with a capac-

itor (0.1µF to 1µF ceramic) in close proximity to the IC.

VSNS[A/B][1:0]M: Negative Output Voltage Sense Inputs.

These pins must still be properly connected on slave

channels for accurate output current telemetry.

VSNS[A/B][1:0]P: Positive Output Voltage Sense Inputs.

These pins must still be properly connected on slave

channels for accurate output current telemetry.

CS[A/B][1:0]M: Current Sense Amplifier Inputs. These (–)

inputs to the amplifiers are normally connected to the low

side of a DCR sensing network or output current sense

resistor for each phase.

CS[A/B][1:0]P: Current Sense Amplifier Inputs. These

(+) inputs are normally connected to the high side of an

output current sense resistor or the R-C midpoint of a

parallel DCR sense circuit for each phase.

IAVG[A/B][1:0]: Average Current Control Pins. A capac-

itor connected between these pins and IAVGND stores a

voltage proportional to the average output current of the

master channel. PolyPhase control is then implemented

in part by connecting all slave IAVG pins together to the

master IAVG output. This pin should be left open on chan-

nels that control single-phase outputs. Operating voltage

range is GND to 2.1V.

FB[A/B][1:0]: Error Amplifier Inverting Inputs. These pins

provide an internally scaled version of the output voltage

for use in loop compensation.

GND: Ground. All GND balls must be soldered to a suitable

PCB copper ground plane for proper electrical operation

and to obtain the specified package thermal resistance.

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