LTC3884 datasheet(22/26 Pages) AD

22 / 26 page

LTC7883

Rev. 0

For more information www.analog.com

Two 100μF SUNCON capacitors and four 22μF ceramic

capacitors are selected to provide acceptable input AC

impedance against the designed converter ripple current.

Ten 220μF ceramic capacitors are chosen for the output to

maintain supply regulation during severe transient condi-

tions and to minimize output voltage ripple.

The power block provides its own output current monitor

signals for use by the LTC7883. The interface network,

shown in detail for differential input CSA1, is also repli-

cated for the other three channels. These remove high

frequency noise from the power block outputs and scale

those signals to be compatible with the LTC7883 inputs. A

fixed common mode reference voltage is required for the

power block –CS[4:1] outputs. A filtered resistor divider

from VDD33 (10k/12.1k/4.3μF) fulfills this requirement,

driving the negative side of the differential current sense

(CSx) signals.

External temperature sense will employ an accurate ∆VBE

method. Q1 serves to sense the temperature of the PCB

as close to the power block as physically possible, and

the 10nF filter capacitor should be placed with the BJT.

Unused TSNS inputs are loaded with 2.74k to produce

a benign reading of about 25ºC with factory EEPROM

settings, if the direct VBE interface mode is selected by

MFR_PWM_MODE_LTC3888-1 on these channels.

Each internal LTC7883 unit must be configured for a

unique address. Resistor configuration is used on the

APPLICATIONS INFORMATION

ASEL pins to program the three most significant PMBus

address bits from EEPROM (MFR_ADDRESS, 0x4X).

Then each unit is given its own unique lower address

nibble, setting the two addresses to 0x4C (Unit A) and

0x4D (Unit B). Ensure the selected addresses do not col-

lide with global addresses or any other specific devices

in the system. Identical MFR_RAIL_ADDRESS should be

set in EEPROM for all four channels to allow single-com-

mand control of common rail parameters such as IOUT_

OC_FAULT_LIMIT. The LTC7883 units also respond to

7-bit global addresses 0x5A and 0x5B. MFR_ADDRESS

and MFR_RAIL_ADDRESS should not be set to either of

these values.

PMBus connections, as well as shared RUN control

and fault propagation (FLT) are provided. SYNC can be

used to synchronize other PWMs to this rail if required.

Recommended PMBus connections and shared PSM con-

nections are shown in more detail in Figure 3.

Pull-ups are provided on all shared open-drain signals

(Figure 1 and Figure 3). The values shown assume a

maximum 100pF line load and PMBus rate of 100kHz.

These pins should not be left floating. Termination to

3.3V ensures the absolute maximum ratings for the pins

are not exceeded. All other operating parameters such

as soft start/stop and desired faults responses are pro-

grammed via PMBus command values stored in internal

LTC7883 EEPROM.

LTC3884 Datasheet(PDF) 22 Page - Analog Devices

LTC3884 Datasheet(HTML) 22 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Datasheet Download

Link URL