LTC4213 datasheet(11/22 Pages) AD

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LTC4213

Rev. A

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APPLICATIONS INFORMATION

ON Function

When VON is below comparator COMP1’s threshold of

0.4V for 80µs, the device resets. The system leaves reset

mode if the ON pin rises above comparator COMP2’s

threshold of 0.8V and the UVLO condition is met. Leaving

reset mode, the GATE pin starts up after a tDEBOUNCE delay

of 60µs. When ON goes below 0.76V, the GATE shuts off

after a 5µs glitch filter delay. The output is discharged by

the external load when VON is in between 0.4V to 0.8V.

At this state, the ON pin can re-enable the GATE if VON

exceeds 0.8V for more than 8µs. Alternatively, the device

resets if the ON pin is brought below 0.4V for 80µs. Once

reset, the GATE pin restarts only after the tDEBOUNCE 60µs

delay at VON rising above 0.8V. To protect the ON pin

from overvoltage stress due to supply transients, a series

resistor of greater than 10k is recommended when the

ON pin is connected directly to the supply. An external

resistive divider at the ON pin can be used with COMP2

to set a supply undervoltage lockout value higher than the

internal UVLO circuit. An RC filter can be implemented at

the ON pin to increase the power-up delay time beyond

the internal 60µs delay.

Gate Function

The GATE pin is held low in reset mode. 60µs after leaving

reset mode, the GATE pin is charged up by an internal

100µA current source. The circuit breaker arms when

VGATE > VSENSEN + ∆VGSARM. In normal mode operation,

the GATE peak voltage is internally clamped to ∆VGSMAX

above the SENSEN pin. When the circuit breaker trips, an

internal MOSFET shorts the GATE pin to GND, turning off

the external MOSFET.

READY Status

The READY pin is held low during reset and at startup. It

is pulled high by an external pull-up resistor 50µs after

the circuit breaker arms. The READY pin pulls low if the

circuit breaker trips or the ON pin is pulled below 0.76V,

or VCC drops below undervoltage lockout.

∆VGSARM and VGSMAX

Each MOSFET has a recommended VGS drive voltage

where the channel is deemed fully enhanced and RDS(ON) is

minimized. Driving beyond this recommended VGS voltage

yields a marginal decrease in RDS(ON) . At start-up, the

gate voltage starts at ground potential. The GATE ramps

past the MOSFET threshold and the load current begins

to flow. When VGS exceeds ∆VGSARM, the circuit breaker

is armed and enabled. The chosen MOSFET should have a

recommended minimum VGS drive level that is lower than

∆VGSARM. Finally, VGS reaches a maximum at ∆VGSMAX.

Trip and Reset Circuit Breaker

Figure 2 shows the timing diagram of VGATE and VREADY

after a fault condition. A tripped circuit breaker can be

reset either by cycling the VCC bias supply below UVLO

threshold or pulling ON below 0.4V for >tRESET. Figure 3

shows the timing diagram for a tripped circuit breaker

being reset by the ON pin.

Calculating Current Limit

The fault current limit is determined by the RDS(ON) of the

MOSFET and the circuit breaker voltage VCB.

ILIMIT =

VCB

RDS(ON)

(2)

The RDS(ON) value depends on the manufacturer’s dis-

tribution, VGS and junction temperature. Short Kelvin-

sense connections between the MOSFET drain and

source to the LTC4213 SENSEP and SENSEN pins are

strongly recommended.

For a selected MOSFET, the nominal load limit current is

given by:

ILIMIT(NOM) =

VCB(NOM)

RDS(ON)(NOM)

(3)

The minimum load limit current is given by:

ILIMIT(MIN) =

VCB(MIN)

RDS(ON)(MAX)

(4)

The maximum load limit current is given by:

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