VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC8131

2.488 Gbit/sec

32:1 SONET/SDH Mux with Clock Generator

Page 2

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

11/9/99

G52249-0, Rev. 3.0

Functional Description

Low Speed Interface

The timing for the low speed parallel interface is based upon the CK78OUT output signal. The intent is to

have the device upstream from the VSC8131 use the CK78OUT clock signal as the timing source for its final

output stage latch. CK78IN is to be driven by CK78OUT, refer to Figure 1. This reduces the setup time of the

the AC Characteristics. The setup and hold time of the data inputs are specified with respect to the rising edge of

CK78IN. D0-D31, CK78OUT, and CK78IN are TTL compatible inputs.

Figure 1: Low Speed System Interface

Parity

A parity check is performed between the parity bit input (PARBIT) and the 32 parallel data inputs (D0-

D31). Even versus odd parity checking is selected with PARMODE. Set PARMODE low to test for odd parity.

Set PARMODE high to test for even parity. The parity error output (PARERR) is set to a logic high when a par-

ity error has occurred. The PARERR signal can be changed from an active high to active low signal by comple-

menting the PARMODE input. PARERR is re-calculated each time new parallel data is clocked in. The newly

calculated PARERR result is clocked out on the rising edge of CK78IN 2 cycles after the data is loaded. PAR-

BIT, PARMODE, and PARERR conform to TTL output levels.

CK78OUT

REFCLK

2.488 GHz

PLL

Divide by 32

VSC8131

Upstream

Device

33

33

D[0:31], PARBIT

CK78IN