AD9887APCB datasheet(35/44 Pages) AD

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AD9887A

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A Logic 1 enables the external CKEXT input pin. In this

mode, the PLL Divide Ratio (PLLDIV) is ignored. The

clock phase adjust (PHASE) is still functional.

The power-up default value is EXTCLK = 0.

Red Clamp Select

A bit that determines whether the red channel is clamped

to ground or to midscale. For RGB video, all three channels

are referenced to ground. For YCbCr (or YUV), the Y

channel is referenced to ground, but the CbCr channels

are referenced to midscale. Clamping to midscale actually

clamps to Pin 118, RCLAMPV.

Table XXII. Red Clamp Select Settings

Clamp

Function

0Clamp to Ground

1Clamp to Midscale (Pin 118)

The default setting for this register is 0.

Green Clamp Select

A bit that determines whether the green channel is clamped

to ground or to midscale.

Table XXIII. Green Clamp Select Settings

Clamp

Function

0Clamp to Ground

1Clamp to Midscale (Pin 109)

The default setting for this register is 0.

Blue Clamp Select

A bit that determines whether the blue channel is clamped

to ground or to midscale.

Table XXIV. Blue Clamp Select Settings

Clamp

Function

0Clamp to Ground

1Clamp to Midscale (Pin 99)

The default setting for this register is 0.

MODE CONTROL 2

Clk Inv Data Output Clock Invert

A control bit for the inversion of the output data clocks,

(Pins 134, 135). This function works only for the digital

interface. When not inverted, data is output on the trail-

ing edge of the data clock. See timing diagrams to see

how this affects timing.

Table XXV. Clock Output Invert Settings

Clk Inv

Function

0Not Inverted

Inverted

The default for this register is 0, not inverted.

Pix Select

This bit selects either 1 or 2 pixels per clock mode for the

digital interface. It determines whether the data comes

out of a single port (even port only), at the full data rate,

or out of two ports (both even and odd ports), at one-half

the full data rate per port. A Logic 0 selects 1 pixel per

clock (even port only). A Logic 1 selects 2 pixels per clock

(both ports). See the Digital Interface Timing Diagrams,

Figures 33 to 36, for a visual representation of this function.

Note: This function operates exactly like the DEMUX

function on the analog interface.

Table XXVI. Pix Select Settings

Pix Select

Function

01 Pixel per Clock

12 Pixels per Clock

The default for this register is 0, 1 pixel per clock.

5, 4

Output Drive

These two bits select the drive strength for the high speed

digital outputs (all data output and clock output pins).

Higher drive strength results in faster rise/fall times and in

general makes it easier to capture data. Lower drive strength

results in slower rise/fall times and helps to reduce EMI

and digitally generated power supply noise. The exact

timing speciﬁcations for each of these modes are speciﬁed

in Table VII.

Table XXVII. Output Drive Strength Settings

Bit 5

Bit 4

Result

High Drive Strength

Medium Drive Strength

Low Drive Strength

The default for this register is 11, high drive strength. (This

option works on both the analog and digital interfaces.)

3 PDO—Power-Down Outputs

A bit that can put the outputs in a high impedance mode.

This applies only to the 48 data output pins and the two

data clock output pins.

Table XXVIII. Power-Down Output Settings

CKINV

Function

0Normal Operation

Three-State

The default for this register is 0. (This option works on

both the analog and digital interfaces.)

Sync Detect Polarity

This pin controls the polarity of the sync detect output

pin (Pin 136).

Table XXIX. Sync Detect Polarity Settings

Polarity

Function

0Activity = Logic 1 Output

1Activity = Logic 0 Output

The default for this register is 0. (This option works on

both the analog and digital interfaces.)

AD9887APCB Datasheet(PDF) 35 Page - Analog Devices

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