AD9887APCB datasheet(24/44 Pages) AD

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AD9887A

7-PIPE DELAY

RGBIN

HSYNC

PXCK

ADCCK

DATACK

ROUTA

HSOUT

GOUTA

Figure 27. 4:2:2 Output Mode

Table VIII. Digital Interface Pin List

Type

Mnemonic

Function

Value

Number

Digital Video Data Inputs

Rx0+

Digital Input Channel 0 True

Rx0–

Digital Input Channel 0 Complement

Rx1+

Digital Input Channel 1 True

Rx1–

Digital Input Channel 1 Complement

Rx2+

Digital Input Channel 2 True

Rx2–

Digital Input Channel Twos Complement

Digital Video Clock Inputs

RxC+

Digital Data Clock True

RxC–

Digital Data Clock Complement

Termination Control

RTERM

Control Pin for Setting the Internal

Termination Resistance

Outputs

Data Enable

3.3 V CMOS

137

HSOUT

HSYNC Output

3.3 V CMOS

139

VSOUT

VSYNC Output

3.3 V CMOS

138

CTL0, CTL1,

Decoded Control Bit Outputs

3.3 V CMOS

46–48

CTL2

HDCP

DDCSCL

HDCP Slave Serial Port Data Clock

3.3 V CMOS

DDCSDA

HDCP Slave Serial Port Data I/O

3.3 V CMOS

MCL

HDCP Master Serial Port Data Clock

3.3 V CMOS

MDA

HDCP Master Serial Port Data I/O

3.3 V CMOS

Power Supply

Main Power Supply

3.3 V

± 5%

PVD

PLL Power Supply

3.3 V

± 5%

VDD

Output Power Supply

3.3 V or 2.5 V

± 5%

GND

Ground Supply

0 V

GND

Ground Supply

0 V

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