AD9887APCB datasheet(39/44 Pages) AD

39 / 44 page

REV. 0

AD9887A

–39–

1B 7-0 Test Register

Must be set to 00H for proper operation.

1C 7-3 Test Bits

Must be set to 0000 0

*** for proper operation.

1C 2

CbCr Output Order

In 4:2:2 mode, the red and blue channels can be interchanged

to help satisfy board layout or timing requirements, but the

green channel must be configured for Y. 1C bit 2 controls

the order that the U/V(CbCr) data is output. If this bit is

high, the Red channel data precedes the Blue channel data.

If this bit is low, the Blue channel data precedes the Red

channel data. See the example in Table LI.

Table LI. 4:2:2 Input/Output Configuration

Input

Channel

Connection

Output Format

Red

V/U if 1C bit 2 = 1,

U/V if 1C bit 2 = 0

Green

Blue

High Impedance

1C 1

Test Bits

Must be set to 0 for standard input sampling.

1C 0

4:2:2 Output Mode Select

4:2:2 mode can be used to reduce the number of data lines

used from 24 down to 16 for applications using YUV,

YCbCr, or YPbPr graphics signals. A timing diagram for

this mode is shown on page 22.

Table LII. 4:2:2 Output Mode Select

Select

Output Mode

4:4:4

4:2:2

2-Wire Serial Control Port

A 2-wire serial interface control port is provided. Up to four

AD9887A devices may be connected to the 2-wire serial interface,

with each device having a unique address.

The 2-wire serial interface comprises a clock (SCL) and a bidirec-

tional data (SDA) pin. The analog flat panel interface acts as a

slave for receiving and transmitting data over the serial inter-

face. When the serial interface is not active, the logic levels on

SCL and SDA are pulled HIGH by external pull-up resistors.

Data received or transmitted on the SDA line must be stable for

the duration of the positive-going SCL pulse. Data on SDA must

change only when SCL is LOW. If SDA changes state while SCL

is HIGH, the serial interface interprets that action as a start or

stop sequence.

There are five components to serial bus operation:

1. Start signal

2. Slave address byte

3. Base register address byte

4. Data byte to read or write

5. Stop signal

When the serial interface is inactive (SCL and SDA are HIGH),

communications are initiated by sending a start signal. The start

signal is a HIGH-to-LOW transition on SDA, while SCL is

HIGH. This signal alerts all slaved devices that a data transfer

sequence is coming.

The ﬁrst eight bits of data transferred after a start signal comprising

of a 7-bit slave address (the ﬁrst seven bits) and a single R/

W bit

(the eighth bit). The R/

W bit indicates the direction of data trans-

fer, read from (1) or write to (0) the slave device. If the transmitted

slave address matches the address of the device (set by the state of

the SA1-0 input pins in Table LIII), the AD9887A acknowledges

by bringing SDA low on the ninth SCL pulse. If the addresses do

not match, the AD9887A does not acknowledge.

Table LIII. Serial Port Addresses

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(MSB)

01100

01101

01110

01111

Data Transfer via Serial Interface

For each byte of data read or written, the MSB is the ﬁrst bit of

the sequence.

If the AD9887A does not acknowledge the master device during

a write sequence, the SDA remains HIGH so the master can

generate a stop signal. If the master device does not acknowledge

the AD9887A during a read sequence, the AD9887A interprets

this as “end of data.” The SDA remains HIGH so the master

can generate a stop signal.

Writing data to speciﬁc control registers of the AD9887A requires

that the 8-bit address of the control register of interest be written

after the slave address has been established. This control register

address is the base address for subsequent write operations. The

base address autoincrements by one for each byte of data written

after the data byte intended for the base address. If more bytes are

transferred than there are available addresses, the address will not

increment and will remain at its maximum value of 1Dh. Any base

address higher than 1Dh will not produce an acknowledge signal.

Data is read from the control registers of the AD9887A in a similar

manner. Reading requires two data transfer operations.

The base address must be written with the R/

W bit of the slave

address byte LOW to set up a sequential read operation.

Reading (the R/

W bit of the slave address byte HIGH) begins at

the previously established base address. The address of the read

To terminate a read/write sequence to the AD9887A, a stop

signal must be sent. A stop signal comprises a LOW-to-HIGH

transition of SDA while SCL is HIGH. The timing for the

read/write operations is shown in Figure 37; a typical byte transfer

is shown in Figure 38.

A repeated start signal occurs when the master device driving the

serial interface generates a start signal without ﬁrst generating a

stop signal to terminate the current communication. This is used

to change the mode of communication (read, write) between the

slave and master without releasing the serial interface lines.

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