AD9887APCB datasheet(13/44 Pages) AD

13 / 44 page

REV. 0

AD9887A

–13–

Outputs

RED A

Data Output, Red Channel, Port A/EVEN

RED B

Data Output, Red Channel, Port B/ODD

GREEN A

Data Output, Green Channel, Port A/EVEN

GREEN B

Data Output, Green Channel, Port B/ODD

BLUE A

Data Output, Blue Channel, Port A/EVEN

BLUE B

Data Output, Blue Channel, Port B/ODD

These are the main data outputs. Bit 7 is the MSB.

Each channel has two ports. When the part is

operated in single-channel mode (DEMUX = 0),

all data are presented to Port A, and Port B is

placed in a high impedance state.

Programming DEMUX to 1 established dual-

channel mode, wherein alternate pixels are

presented to Port A and Port B of each channel.

These will appear simultaneously, two pixels

presented at the time of every second input

pixel, when PAR is set to 1 (parallel mode).

When PAR = 0, pixel data appear alternately

on the two ports, one new sample with each

incoming pixel (interleaved mode).

In dual-channel mode, the ﬁrst pixel after

HSYNC is routed to Port A. The second pixel

goes to Port B, the third to A, etc.

The delay from pixel sampling time to output is

ﬁxed. When the sampling time is changed by

adjusting the PHASE register, the output timing is

shifted as well. The DATACK,

DATACK, and

HSOUT outputs are also moved, so the timing

relationship among the signals is maintained.

DATACK

Data Output Clock

DATACK

Data Output Clock Complement

Differential data clock output signals to be

used to strobe the output data and HSOUT

into external logic.

They are produced by the internal clock gen-

erator and are synchronous with the internal

pixel sampling clock.

When the AD9887A is operated in single-

channel mode, the output frequency is equal

to the pixel sampling frequency. When operating

in dual-channel mode, the clock frequency is

one-half the pixel frequency.

When the sampling time is changed by adjusting

the PHASE register, the output timing is shifted

as well. The Data, DATACK,

DATACK, and

HSOUT outputs are all moved, so the timing

relationship among the signals is maintained.

Power Supply

Main Power Supply

These pins supply power to the main elements

of the circuit. It should be ﬁltered to be as

quiet as possible.

VDD

Digital Output Power Supply

These supply pins are identiﬁed separately

from the VD pins so special care can be taken

to minimize output noise transferred into the

sensitive analog circuitry.

If the AD9887A is interfacing with lower-

voltage logic, VDD may be connected to a lower

supply voltage (as low as 2.2 V) for compatibility.

PVD

Clock Generator Power Supply

The most sensitive portion of the AD9887A

is the clock generation circuitry. These pins

provide power to the clock PLL and help the

user design for optimal performance. The

designer should provide noise-free power to

these pins.

GND

Ground

The ground return for all circuitry on-chip. It is

recommended that the application circuit

board have a single, solid ground plane.

THEORY OF OPERATION (INTERFACE DETECTION)

Active Interface Detection and Selection

The AD9887A includes circuitry to detect whether an interface

is active (see Table III).

For detecting the analog interface, the circuitry monitors the

presence of HSYNC, VSYNC, and Sync-on-Green. The result of

the detection circuitry can be read from the 2-wire serial interface

bus at Address 11H Bits 7, 6, and 5, respectively. If one of these

sync signals disappears, the maximum time it takes for the

circuitry to detect it is 100 ms.

There are two stages for detecting the digital interface. The ﬁrst

stage searches for the presence of the digital interface clock. The

circuitry for detecting the digital interface clock is active even

when the digital interface is powered down. The result of this

detection stage can be read from the 2-wire serial interface bus at

Address 11H Bit 4. If the clock disappears, the maximum time it

takes for the circuitry to detect it is 100 ms. Once a digital inter-

face clock is detected, the digital interface is powered up and the

second stage of detection begins. During the second stage, the

circuitry searches for 32 consecutive DEs. Once 32 DEs are

found, the detection process is complete.

There is an override for the automatic interface selection. It is

the AIO bit (active interface override). When the AIO bit is set

to Logic 0, the automatic circuitry will be used. When the AIO

bit is set to Logic 1, the AIS bit will be used to determine the

active interface rather than the automatic circuitry.

AD9887APCB Datasheet(PDF) 13 Page - Analog Devices

AD9887APCB Datasheet(HTML) 13 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL