LTC3871 datasheet(11/24 Pages) AD

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LTC7106

Rev A

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OPERATION

GPO

GPO is a general purpose open-drain output pin, which

can be set by PMBus command. It is designed to turn on/

off the DC/DC regulator by connecting GPO to the RUN

pin of the regulator. Once GPO is set high, it stays high

even if the EN pin goes low as long as the device is not

power cycled.

ADDRESS

The PMBus address is selected by ASEL0 and ASEL1

pins. Each pin has three states: high, low and floating.

The possible PMBus addresses are shown in Table 3.

Table 3. Address Selection

ASEL1

ASEL0

PMBus ADDRESS

GND

VDD

GND

FLOAT

VDD

GND

VDD

FLOAT

GND

FLOAT

VDD

FLOAT

PMBus SERIAL INTERFACE

The LTC7106 serial interface is a PMBus-compliant slave

device and can operate at any frequency between 10kHz

and 400kHz. In addition the LTC7106 always responds to

the global broadcast address of 0x5A or 0x5B (7-bit). The

serial interface supports the following protocols defined

in the PMBus specifications: 1) send command, 2) write

byte, 3) group, 4) read byte and 5) read word. The PMBus

write operations are not acted upon until a complete valid

messageisreceivedbytheLTC7106includingtheSTOPbit.

Communication Failure

Attempts to access unsupported commands or writing

invalid data to supported commands will result in a CML

fault. The CML bit is set in the STATUS_BYTE command

and the ALERT pin is pulled low.

Device Addressing

TheLTC7106offersfourdifferenttypesofaddressingover

the PMBus interface, specifically: 1) global, 2) device, 3)

rail addressing and 4) alert response address (ARA).

Global addressing provides a means of the PMBus master

to address all LTC7106 devices on the bus. The LTC7106

global addresses are fixed 0x5A or 0x5B (7 bit) or 0xB4

or 0xB6 (8 bit) and cannot be disabled.

Device addressing provides the standard means of

the PMBus master communicating with a single instance

of a LTC7106. The value of the device address is set by

the ASEL0/ASEL1 configuration pins. Rail addressing

provides a means of the PMBus master addressing a

set of channels connected to the same output rail, simul-

taneously. This is similar to global addressing, however,

the PMBus address can be dynamically assigned by

using the MFR_RAIL_ADDRESS command. It is recom-

mendedthatrailaddressingshouldbelimitedtocommand

write operations.

All four means of PMBus addressing require the user to

employ disciplined planning to avoid addressing conflicts.

Fault Status

The STATUS_BYTE and ALERT pin provide fault status

information of the LTC7106 to the host.

Bus Timeout Failure

The LTC7106 implements a timeout feature to avoid hang-

ing the serial interface. The data packet timer begins at the

first START event before the device address write byte.

Data packet information must be completed within 25ms

or the LTC7106 will tri-state the bus and ignore the given

data packet. Data packet information includes the device

address byte write, command byte, repeat start event

(if a read operation), device address byte read (if a read

operation), and all data bytes.

The user is encouraged to use as high a clock rate as

possible to maintain efficient data packet transfer be-

tween all devices sharing the serial bus interface. The

LTC7106 supports the full PMBus frequency range from

10kHz to 400kHz.

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