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PI6C410 Datasheet(PDF) 1 Page - Pericom Semiconductor Corporation |
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PI6C410 Datasheet(HTML) 1 Page - Pericom Semiconductor Corporation |
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1 / 16 page  1 PS8734A 09/02/04 Product Features • 14.318 MHz Crystal Input • Selectable of 100, 133, 166, 200, 266, 333, and 400MHz CPU Output Frequencies • SMBus: Power Management Control • Spread Spectrum support (-0.5% down spread) • Packaging (Pb-free & Green available): -56-Pin SSOP (V) -56-Pin TSSOP (A) Output Features • Two Pairs of Differential CPU Clocks • One selectable of CPU/SRC Clock • Six Pairs of SRC Clocks • Nine PCI Clocks • One 48 MHz USB clock • One REF clock • One 96 MHz Differential clock Product Description PI6C410 is a high-speed, low-noise clock generator designed to work with Intel Desktop PCI-Express Chipset. Spread Spectrum PLL based clock generator reduce EMI emis- sion and support a wide range of frequencies. Jitter Performance • < 85ps Cycle to Cycle CPU clock jitter • < 350ps Cycle to Cycle 48MHz clock jitter • < 500ps Cycle to Cycle PCI clock jitter • < 125ps Cycle to Cycle SRC clock jitter • < 1000ps Cycle to Cycle REF clock jitter Skew Performance • < 100ps Output to output CPU clock skew • < 500ps Output to output PCI clock skew • < 250ps Output to output SRC clock skew Logic Block Diagram Pin Description PI6C410 Clock Generator for Intel PCI-Express Desktop Chipset Div Div PLL 1 XTAL OSC C O N T R O L SMBus Logic REF DOT_96 DOT 96# USB_48 PCI [0:5] PCIF[0:2] SRC [1:6] SRC [1:6]# CPU[0:1] CPU[0:1]# XTAL_IN XTAL_OUT SDA SCL FS_A FS_B / TEST_MODE VTT_PWRGD# / PWRDWN CPU2_ITP / SRC7 CPU2_ITP# / SRC7# Div PLL 2 FS_C / TEST_SEL /2 PCIF_0 / ITP_EN PCI_2 PCI_1 PCI_0 FS_C / TEST_SEL REF VSS_REF XTAL_IN XTAL_OUT VDD_REF SDA SCL VSS_CPU CPU_0 CPU_0# VDD_CPU CPU_1 CPU_1# IREF VSS_A VDD_A CPU2_ITP / SRC7 CPU2_ITP# / SRC7# VDD_SRC SRC_6 SRC_6# SRC_5 SRC_5# VSS_SRC VDD_PCI VSS_PCI PCI_3 PCI_4 PCI_5 VSS_PCI VDD_PCI PCIF_0 / ITP_EN PCIF_1 PCIF_2 VDD_48 USB_48 VSS_48 DOT_96 DOT_96# FS_B / TEST_MODE VTT_PWRGD# / PWRDWN FS_A SRC_1 SRC_1# VDD_SRC SRC_2 SRC_2# SRC_3 SRC_3# SRC_4 SRC_4# VDD_SRC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 |
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