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Data Sheet

AD3551R

THEORY OF OPERATION

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Rev. 0 | 23 of 60

CUSTOM OUTPUT VOLTAGE SPAN

In addition to the predefined output span ranges configured

via the CH0_OUTPUT_RANGE register, the output span range

can be customized by programming the offset and gain reg-

isters in conjunction with the external feedback resistor. The

CH0_RANGE_OVERRIDE bit must be set in the CH0_GAIN regis-

ter to override the predefined range and offset values. Gain is

configured as a combination of two parameters, CH0_GAIN_SCAL-

ING_P and CH0_GAIN_SCALING_N in the CH0_GAIN register.

The absolute value of the offset is configured in the CH0_OFFSET

ITY bit in the CH0_GAIN register.

The bounds of the output span are defined in the following equa-

tions:

Zero−Scale Output Voltage VOUT_ZS =2.5

−1.6×RF× GainP−Offset

Full−Scale Output Voltage VOUT_FS =2.5+1

.6×RF× GainN+Offset

where:

RF = 1.610938 for RFB1_0, 3.228125 for RFB2_0, and 6.488125

for RFB4_0

GainP= 1

2CH0_GAIN_SCALING_P

GainN= 1

2CH0_GAIN_SCALING_N

Offset=OFFSET_POLARITY × CH0_OFFSET

512

OFFSET_POLARITY = 1 if CH0_OFFSET_POLARITY = 0 and −1 if

CH0_OFFSET_POLARITY = 1

Note that a given output span range can be configured in multiple

ways, by combining a larger RFBx_0 value with a smaller GainN

and GainP value or the other way around. A smaller GainN or GainP

value results in lower power consumption, but a larger RFBx_0

value is required to achieve the same output, which results in

higher noise density.

TRANSFER FUNCTION

The conversion of the digital code to the DAC output current follows

a linear relation with the code in plain binary. The ideal output

current, in mA, is given by the following equation:

IOUTx=1.6× GainP−Offset− D216×

GainP+GainN

where:

D is the decimal equivalent of the binary code that is loaded in the

DAC register

Offset, GainP, and GainN are according to the definitions given in

the Custom Output Voltage Span section

The conversion of current to voltage is performed in the external

TIA. If the internal feedback resistor is used, the output voltage

follows the following equation:

VOUTx=VCMx−RF×IOUTx

where:

VCMx is the common-mode voltage at the VCMx pin that is connected

to the noninverting input of the TIA, nominally 2.5 V

RF is according to the definition given in the Custom Output Voltage

Span section.

VREF

The AD3551R has an internal 2.5 V voltage reference with a

3 ppm/°C temperature coefficient that is enabled at power-up. The

VREF pin is in high impedance at power-up to avoid electrical

problems. If the internal reference must be used externally, the

REFERENCE_VOLTAGE_SEL bits in the REFERENCE_CONFIG

Table 9.

When the external reference is selected, the VREF pin behaves as

an input.

Table 9. Voltage Reference Selection

REFERENCE_VOLTAGE_SEL

Source

VREF I/O

Internal

Floating

Internal

2.5 V

External

Input

External

Input

SPI REGISTER MAP ACCESS

SPI Frame Synchronization

The CS signal frames data during an SPI transaction. A falling edge

on CS enables the digital interface and initiates an SPI transaction.

Each SPI transaction consists of at least one instruction phase and

data phase, as described in the Instruction Phase section and the

Data Phase section. For all SPI transactions, data is aligned MSB

first. Deasserting CS during an SPI transaction terminates part or

all of the data transfer and disables the digital interface. If CS is

deasserted (returned high) after one or more register addresses

are issued, those registers are written or read, but any partially

addressed register is ignored. Figure 67 and Figure 68 outline the

stages of a basic SPI write and read frame, respectively, for the

AD3551R in register mode.

Detailed timing diagrams for register read and write operations are

shown in Figure 2 and Figure 10. The timing specification is given

in the Timing Characteristics section.

The AD3551R SPI protocol is flexible and can be configured to suit

the needs of a variety of digital hosts. Data from multiple registers

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