AD8065 datasheet(29/60 Pages) AD

29 / 60 page

Data Sheet

AD3551R

THEORY OF OPERATION

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Rev. 0 | 29 of 60

When using single instruction mode, every CRC code in an SPI

frame uses 0xA5 as the seed value to prevent stuck at fault

conditions for Address 0x00.

When using streaming mode, the first CRC code in an SPI frame

also uses 0xA5 as the seed value, but subsequent CRC codes in

the same frame are calculated using the least significant byte of the

value.

Because enabling the CRC in single SPI (classic) mode requires

that the SDO pin shifts out the CRC calculated by the AD3551R,

the transaction must respect the limitations of a read operation,

which is that DDR is disabled.

In dual and quad SPI modes, the CRC is appended at the end of

the byte or multibyte register transaction but the CRC is generated

only by the controller (write) or by the AD3551R (read), as shown in

Figure 77 and Figure 78.

When CRC error detection is enabled, do not use streaming mode,

including looping, if the range of registers being addressed includes

unused or reserved registers.

Figure 77. Dual SPI Transaction with CRC

Figure 78. Quad SPI Transaction with CRC

AD8065 Datasheet(PDF) 29 Page - Analog Devices