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AM2732 Datasheet(PDF) 62 Page - Texas Instruments |
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AM2732 Datasheet(HTML) 62 Page - Texas Instruments |
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62 / 97 page ![]() REF_CLK (PRCM) rmiin_txd1−rmiin_txd0, rmiin_txen (Outputs) SPRS8xx_GMAC_RMIITX_06 RMII7 RMII8 RMII9 RMII11 RMII10 Figure 7-13. GMAC Transmit Interface Timing RMIIn Operation 7.11.3.3.8 RMII Receive Clock Timing Requirements NO. MIN MAX UNIT RMII1 tc(REF_CLK) Cycle time, REF_CLK 20 ns RMII2 tw(REF_CLKH) Pulse duration, REF_CLK high 7 13 ns RMII3 tw(REF_CLKL) Pulse duration, REF_CLK low 7 13 ns RMII4 ttt(REF_CLK) Transistion time, REF_CLK 3 ns 7.11.3.3.9 RMII Receive Data and Control Timing Requirements NO. MIN MAX UNIT RMII5 tsu(RXD-REF_CLK) Setup time, receive selected signals valid before REF_CLK 4 ns tsu(CRS_DV-REF_CLK) tsu(RX_ER-REF_CLK) RMII6 th(REF_CLK-RXD) Hold time, receive selected signals valid after REF_CLK 2 ns th(REF_CLK-CRS_DV) th(REF_CLK-RX_ER) REF_CLK (PRCM) RMII5 RMII6 rmiin_rxd1− rmin_rxer rmiin_rxd0, rmiin_crs, (inputs) SPRS8xx_GMAC_RMIIRX_05 RMII1 RMII3 RMII2 RMII4 Figure 7-14. GMAC Receive Interface Timing RMIIn operation 7.11.3.3.10 MII Transmit Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT 1 td(TX_CLK-TXD) Delay time, miin_txclk to transmit selected signals valid 0 25 ns td(TX_CLK-TX_EN) td(TX_CLK-TX_ER) AM2732, AM2732-Q1 SWRS245A – DECEMBER 2021 – REVISED FEBRUARY 2022 www.ti.com 62 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM2732 AM2732-Q1 |
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