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VSC7217 Datasheet(PDF) 29 Page - Vitesse Semiconductor Corporation

Part # VSC7217
Description  Multi-Gigabit Interconnect Chip
PDF  36 Pages
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Manufacturer  VITESSE [Vitesse Semiconductor Corporation]
Direct Link  http://www.vitesse.com
Logo VITESSE - Vitesse Semiconductor Corporation

VSC7217 Datasheet(HTML) 29 Page - Vitesse Semiconductor Corporation

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© VITESSE SEMICONDUCTOR CORPORATION
Page 29
6/14/00
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC7217
Multi-Gigabit Interconnect Chip
G52325-0, Rev. 3.0
Table 17: Pin Description
Pin
Name
I/O
Type
Pin Description
6Y, 8U,
7W, 5Y,
7V, 7U,
6W, 5W
TA(7:0)
I
TTL
Transmit Data for Channel n. Synchronous to REFCLK, TBCA or TBCn.
11U, 11W,
10Y, 10W,
10U, 10V,
9Y, 9W
TB(7:0)
I
TTL
Transmit Data for Channel n. Synchronous to REFCLK, TBCB or TBCn.
12A, 11C,
11D, 10A,
10B, 10D,
10C, 9A
TC(7:0)
I
TTL
Transmit Data for Channel n. Synchronous to REFCLK, TBCC or TBCn.
8D, 8C,
7B, 5A,
7D, 6B,
6C, 5B
TD(7:0)
I
TTL
Transmit Data for Channel n. Synchronous to REFCLK, TBCD or TBCn.
7Y
11V
12B
6A
C/DA
C/DB
C/DC
C/DD
I
TTL
Control/Data for Channel n. If KCHAR=C/Dn=LOW, then Tn(7:0) is used
to generate transmit data. If KCHAR=C/Dn=HIGH, then special Kxx.x
characters are transmitted based upon the value of Tn(7:0). If
KCHAR=LOW and C/Dn=HIGH, IDLE characters are transmitted.
When ENDEC=LOW, this is equivalent to data bit Tn8.
8Y
12Y
12C
8B
WSENA
WSENB
WSENC
WSEND
I
TTL
Word Sync ENable for Channel n. Asserted HIGH for one cycle to initiate
transmission of the Word Sync Sequence as defined in Figure 5 and related
text.
When ENDEC=LOW, this is equivalent to data bit Tn9.
9U
9V
9B
9C
TBCA
TBCB
TBCC
TBCD
I
TTL
Transmit Byte Clock for Channel n. Optional input data timing reference for
Tn(7:0), WSENn and C/Dn.
12W
KCHAR
I
TTL
Special Kxx.x CHARacter Enable. When C/Dn is HIGH, KCHAR controls
data sent to the transmitter. When LOW, IDLE characters are sent. When
HIGH, Kxx.x special characters are sent as encoded on Tn(7:0). This is
intended to be a static input and cannot be changed on a cycle-by-cycle
basis.
When ENDEC=LOW, this is equivalent to ENCDET.
5D
6D
4B
TMODE0
TMODE1
TMODE2
I
TTL
Transmit Input Data Timing MODE. Determines the timing reference for
Tn(7:0), WSENn and C/Dn on all channels as defined in Table 1.
20R
17V
18B
20H
TBERRA
TBERRB
TBERRC
TBERRD
O
TTL
Transmit Buffer ERRor for Channel n. When HIGH indicates that the
elastic limit of the transmit input skew buffer was exceeded, output timing is
same as Rn(7:0). A LOW indicates correct reception of the256-bye
incrementing pattern in BIST mode.



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