71M6543GHT datasheet(55/75 Pages) MAXIM

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71M6543GT/71M6543GHT

Energy Meter ICs

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Table 13. I/O RAM Locations in Alphabetical Order (continued)

NAME

LOCATION RSTWK DIR

DESCRIPTION

FIR_LEN[1:0]

210C[2:1]

0 R/W

DeterminesthenumberofADCcyclesintheADCdecimationFIRfilter.

PLL_FAST = 1:

FIR_LEN[1:0]

ADC CYCLES

141

288

384

PLL_FAST = 0:

FIR_LEN[1:0]

ADC CYCLES

135

276

Not allowed

The ADC LSB size and full-scale values depend on the FIR_LEN[1:0] setting.

FLSH_BANK

SFR B6[1:0] 01 01 R/W

Flash Bank Selection

FLSH_BANK[1:0]

ADDRESS RANGE FOR LOWER

BANK (0x0000–0x7FFF)

ADDRESS RANGE FOR UPPER

BANK (0x8000–0x7FFF)

0x0000–0x7FFF

0x8000–0x7FFF

0x0000–0x7FFF

0x10000–0x17FFFF

0x0000–0x7FFF

0x18000–0x1FFFF

FLSH_ERASE[7:0] SFR 94[7:0] 0

0 W

Flash Erase Initiate

FLSH_ERASEisusedtoinitiateeithertheFlashMassErasecycleortheFlashPageErasecycle.Specificpatterns

are expected for FLSH_ERASE in order to initiate the appropriate Erase cycle.

(default = 0x00).

0x55 = Initiate Flash Page Erase cycle. Must be proceeded by a write to FLSH_PGADR[6:0] (SFR 0xB7[7:1]).

0xAA = Initiate Flash Mass Erase cycle. Must be proceeded by a write to FLSH_MEEN and the ICE port must be

enabled.

Any other pattern written to FLSH_ERASE has no effect.

FLSH_MEEN

SFR B2[1]

0 W

Mass Erase Enable

0 = Mass Erase disabled (default).

1 = Mass Erase enabled.

Must be re-written for each new Mass Erase cycle.

FLSH_PEND

SFR B2[3]

0 R Indicatesthatatimedflashwriteispending.Ifanotherflashwriteisattempted,itisignored.

FLSH_PGADR[6:0] SFR B7[7:1] 0

0 W

Flash Page Erase Address

Flash Page Address (page 0 thru 63) that is erased during the Page Erase cycle. (default = 0x00).

Must be re-written for each new Page Erase cycle.

FLSH_PSTWR

SFR B2[2]

0 R/W

Enablestimedflashwrites.When1,andifCE_E=1,flashwriterequestsarestoredinaone-elementdeepFIFO

and are executed when CE_BUSY falls. FLSH_PEND can be read to determine the status of the FIFO. If FLSH_

PSTWR=0orifCE_E=0,flashwritesareimmediate.

FLSH_PWE

SFR B2[0]

0 R/W

Program Write Enable

0 = MOVX commands refer to External RAM Space, normal operation (default).

1 = MOVX @DPTR,A moves A to External Program Space (Flash) @ DPTR.

Thisbitisautomaticallyresetaftereachbytewrittentoflash.Writestothisbitareinhibitedwheninterruptsare

enabled.

FLSH_RDE

2702[2]

–

– R IndicatesthattheflashmaybereadbyICEorSPIslave.FLSH_RDE=(!SECURE)

FLSH_UNLOCK

[3:0]

2702[7:4]

0 R/W Mustbea‘2’toenableanyflashmodification.SeethedescriptionofFlashsecurityformoredetails.

FLSH_WRE

2702[1]

–

– R IndicatesthattheflashmaybewrittenthroughICEorSPIslaveports.

IE_XFER

IE_RTC1S

IE_RTC1M

IE_TCTEMP

IE_RTCT

IE_SPI

IE_EEX

IE_XPULSE

IE_YPULSE

IE_WPULSE

IE_VPULSE

SFR E8[0]

SFR E8[1]

SFR E8[2]

SFR E8[3]

SFR E8[4]

SFR F8[7]

SFR E8[7]

SFR E8[6]

SFR E8[5]

SFR F8[4]

SFR F8[3]

0 R/W

Interruptflagsforexternalinterrupts2,5,and6.Theseflagsmonitorthesourceoftheint2,int5,andint6interrupts

(externalinterruptstotheMPUcore).Theseflagsaresetbyhardwareandmustbeclearedbythesoftware

interrupthandler.TheIEX2(SFR0xC0[1])andIEX6(SFR0xC0[5])interruptflagsareautomaticallyclearedby

the MPU core when it vectors to the interrupt handler. IEX2 and IEX6 must be cleared by writing zero to their

corresponding bit positions in SFR 0xC0, while writing ones to the other bit positions that are not being cleared.

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