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A5000 Datasheet(PDF) 9 Page - NXP Semiconductors

Part # A5000
Description  Edge Lock Secure Authenticator
PDF  26 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

A5000 Datasheet(HTML) 9 Page - NXP Semiconductors

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NXP Semiconductors
A5000
Edge Lock Secure Authenticator
5 Communication interfaces
The communication with the A5000 authenticator follows a command / response concept.
This means that, after sending the full command to the authenticator all data needs to be
retrieved fully until the next command can be sent.
5.1 I2C Interfaces
The A5000 has one I2C interface supporting target.
The I2C target interface is used by the host controller to send arbitrary APDUs to the
device. The I2C interface is using the Smartcard T=1 over I2C protocol.
The default target address of the A5000 is configured to 0x48.
aaa-037450
1
0
0
1
target address
0
0
0 R/W
Figure 3. Target address
5.1.1 Supported I2C frequencies
The A5000 I2C target interface supports the I2C fast-speed mode with a maximum SCL
clock of up to 1 MHz.
5.1.2 Default I2C Communication Parameters
The default I2C interface parameters of the A5000 devices are chosen with the highest
compatibility in mind:
• The used I2C protocol is detected automatically on the first received frame amongst the
two possible protocols:
– NXP SE05x T=1 Over I2C Specification. See [1].
– APDU Transport over SPI/I2C v1.0 | GPC_SPE_172. See [4].
• Power down can be explicitly requested by the host via an "End of APDU session
request" (according to [1]) respectively "RELEASE request" from GP T=1oI2C [4].
6 Power-saving modes
The device provides two power-saving operation modes. The Power-down mode (with
state retention) and the Deep Power-down mode (no state retention). These modes are
activated via pad ENA (Deep Power-down mode) or by the SW (Power-down mode).
6.1 Power-down mode
The Power-down mode has the following properties:
• All internal clocks are frozen
• CPU enters power-saving mode with program execution being stopped
• CPU registers keep their contents
A5000
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2022. All rights reserved.
Product data sheet
Rev. 1.0 — 28 March 2022
667609
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