ADSP-SC595 datasheet(76/134 Pages) AD

76 / 134 page

Rev. PrD

Page 76 of 134

May 2022

ADSP-SC595/SC596/SC598

Preliminary Technical Data

Serial Ports (SPORTs)

To determine whether a device is compatible with the SPORT at clock speed n, the following specifications must be confirmed: frame sync

delay and frame sync setup and hold; data delay and data setup and hold; and serial clock (SPTx_CLK) width. In Figure 14, either the ris-

ing edge or the falling edge of SPTx_A/BCLK (external or internal) can be used as the active sampling edge.

When externally generated, the SPORT clock is called fSPTCLKEXT:

When internally generated, the programmed SPORT clock (fSPTCLKPROG) frequency in megahertz is set by the following equation:

where CLKDIV is a field in the SPORT_DIV register that can be set from 0 to 65,535.

Table 43. SPORTs—External Clock1

1 Specifications apply to all four SPORTs.

All specifications are based on simulation data and are subject to change without notice.

Parameter

Min

Max

Unit

Timing Requirements

tSFSE

Frame Sync Setup Before SPTx_CLK

(Externally Generated Frame Sync in Either Transmit or Receive

Mode)2

2 Referenced to sample edge.

2ns

tHFSE

Frame Sync Hold After SPTx_CLK

(Externally Generated Frame Sync in Either Transmit or Receive

Mode)2

3ns

tSDRE

Receive Data Setup Before Receive SPTx_CLK2

2ns

tHDRE

Receive Data Hold After SPTx_CLK2

3ns

tSPTCLKW

SPTx_CLK Width3

3 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the ideal maximum external SPTx_CLK.

For the external SPTx_CLK ideal maximum frequency, see the fSPTCLKEXT specification in Table 22.

0.5 × tSPTCLKEXT – 1.5

tSPTCLK

SPTx_CLK Period3

tSPTCLKEXT – 1.5

Switching Characteristics

tDFSE

Frame Sync Delay After SPTx_CLK

(Internally Generated Frame Sync in Either Transmit or Receive

Mode)4

4 Referenced to drive edge.

tHOFSE

Frame Sync Hold After SPTx_CLK

(Internally Generated Frame Sync in Either Transmit or Receive

Mode)4

2ns

tDDTE

Transmit Data Delay After Transmit SPTx_CLK4

tHDTE

Transmit Data Hold After Transmit SPTx_CLK4

2ns

tSPTCLKEXT

fSPTCLKEXT

-----------------

fSPTCLKPROG

fSCLK0

CLKDIV



------------------------

tSPTCLKPROG

fSPTCLKPROG

--------------------

ADSP-SC595 Datasheet(PDF) 76 Page - Analog Devices

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